The ARINC 664 (AFDX) End System DO-254 IP Core (AFDX ES IP) implements an AFDX End System as specified in ARINC 664 Part 7 “Avionics Full-Duplex Switched Ethernet (AFDX) Network”.
The AFDX ES IP supports MII, RMII, GMII or SGMII as PHY interfaces. Therefore, it is able to transmit and receive at 10 Mbps, 100 Mbps or 1000 Mbps, making full usage of the bandwidth.
The communication with the host is done through two AXI Interfaces: an AXI4-Lite Subordinate allows the host to access the status, control and configuration, while an AXI4 Manager allows the host to read/write messages using AXI burst transfers.
The AFDX ES IP uses the internal memory for buffering the transmitted and received messages (no external memory is needed). The size of the buffers depends on the resources available in the target device.
The AFDX ES IP is accompanied by a set tools to generate the AFDX ES configuration.
The AFDX ES IP has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit.
