Area-efficient decision tree ensemble evaluation core based on parallel evaluation of ensemble members

Overview

So_ip_edte_un_p core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consisting from decision tree with the previously defined structure directly in hardware. It implements every DT from the ensemble as a separate module using an area efficient sequential architecture in order to save logic resources.
So_ip_edte_un_p core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_edte_un_p design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_edte_un_p core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.

Key Features

  • Implements ensemble classifier comprised from DTs with previously defined structure
  • Each ensemble member is implemented as a separate module using area efficient sequential architecture
  • Supports classification problems that are defined by numerical attributes only
  • DTs with univariate or multivariate tests are supported
  • DTs with nonlinear tests are supported
  • Ensemble can be composed from a combination of oblique and nonlinear DTs
  • Possibility to alter the implemented DT structure during the actual operation
  • No special IP blocks are needed to implement the core, only memory, adders and multipliers
  • User can specify the number format for all DT parameters in order to achieve the best performance/size ratio after implementation

Deliverables

  • VHDL Source Code or netlis
  • Verification environment with regression suite
  • Technical documentation
  • Installation notes
  • User Manual
  • Datasheet
  • Instantiation templates
  • Reference Design
  • Technical Support
  • IP Core implementation support
  • Variable length maintenance
  • Delivery of IP Core updates, minor and major changes
  • Delivery of documentation updates
  • Telephone & email support

Technical Specifications

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