[Technology]
Process:TSMC 28nm HPM/HPC,
Available metalization technologies: 4X2Y2R and 5X2Y2R
Analog-PLL For Frequency Multiplying
Overview
Key Features
- Including Loop-filter
- VCO operating range : 850MHz - 1700 MHz
- Output frequency range : 850MHz -1700 MHz
- Input frequency range : 9.6MHz - 216MHz
- Multiplying (Output freq. / PFD freq.) : 49 - 127
- Divider : 7bit feedback divider and 3bit input divider
- Power-down Mode
- Multiple outputs with post-divider
- Power-on sequence is constraint-free
- STBY sequence is constraint-free
Block Diagram
Technical Specifications
Foundry, Node
TSMC 28nm HPM/HPC
TSMC
Pre-Silicon:
28nm
HPC
,
28nm
HPM
Related IPs
- Analog PLL For Frequency Multiplying
- Frequency Synthesizer PLL
- Frequency Synthesizable PLL (Vcc=2.5V,Fin=20~50MHz, Fout=50~400MHz, Jitter= +/-150pS)
- Frequency Synthesizable PLL (Vcc=2.5V,Fin=5~50MHz, Fout=50~500MHz, Jitter= +/-100pS)
- Frequency Synthesizable PLL (Vcc=1.8V,Fin=2~40MHz, Fout=40~250MHz, Jitter= +/-120pS)
- Frequency Synthesizable PLL (Vcc=1.8V, Fin=10~40MHz, Fout=200~500MHz, Jitter= +/- 120pS)