The AMBA 5 AHB Verification IP provides an effective & efficient way to verify the components interfacing with AMBA®5 AHB bus of an IP or SoC.
The AMBA 5 AHB VIP is fully compliant with standard AMBA 5 AHB specification from ARM. This VIP is a light weight VIP with easy plug-andplay interface so that there is no hit on the design cycle time.
AMBA AHB 5 Verification IP
Overview
Key Features
- Compliant to AMBA®5 AHB Protocol specifications and AMBA 3 AHB-Lite Verification IP from ARM
- Support for all type of AMBA AHB devices:
- AHB5Master
- AHB5Slave
- Wide range of strict programmable protocol checks
- Bus assertion for all protocol scenarios
- Support bus endianess conversion.
- Fully compliant to inter connect matrix
- Both little & big bus endianness supported. In big endian Byte-invarient and Word-invarient also supported.
- Support for all protocol transfer types, burst transfers and transfer sizes
- All type of memories supported ,like in device memory Device-nE ,Device -E and in normal memory Non-cacheable, Write-through, Write-back type.
- Both secure and non-secure transfer are supported.
- Supports Callback in Master, Slave, Monitor and Scoreboard
- Exclusive transfer supported with exclusive monitoring component.
- Supports stable signal as well as generation of glich in between clock edge as per selected configuration mode
- Complete static and dynamic assertion protocol checks
- Supports wide variety of error injection scenarios
- Parameterized data and address widths
- Support transaction logging with detailed description of each transfer
- Support UVM_ RAL Model
- Configurable Memory.
- Provides detailed performance monitoring for all the transfers.
- Support GUI analyzer for easy debugging
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
- Availability of various Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Provide complete solution and easy integration in IP and SoC environment
Block Diagram

Deliverables
- AMBA 5AHBMaster/Slave Agent
- AMBA 5AHB Bus Monitor and Scoreboard
- Test Environment & Test Suite :
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes
Technical Specifications
Related IPs
- SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
- AMBA 5 AHB Verification IP
- AMBA 5 AHB Bus Verification IP
- SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect