AHB Arbiter IIP

Overview

Key Features

• Compliant with AMBA AHB specification
• Supports configurable number of AHB Master
• Supports configurable number of AHB Slave
• Supports standardized user interface signals for easy integration with any IP
• Round-robin or priority based arbitration selectable per Slave
• Higher throughput and less arbitration overhead between Masters as arbitration is
• done at each Slave port
• Supports all protocol transfer types, burst transfers and response types
• Support for all the transfer sizes
• Supports configurable Endianness of the Data bus
• Supports locked transfers
• Supports early burst termination on receiving Error response from Slave
• Supports two cycle error response in Slave
• Supports response generation with wait states in Slave
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

• The AHB Arbiter is available in Source and netlist products.
• The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.

Technical Specifications