A memory BIST solution which has been optimized for Dolphin memories

Overview

Dolphin Technology now provides a memory BIST solution which has been optimized for Dolphin memories. It supports all Dolphin memory compilers, including SRAM and RF.
- Fully automated MBIST RTL and Gate flow
- Fully supported BIST test, diagnosis and soft/hard repair
- Fully supported eFuse controller for automated hard repair
- Fully supported ICL/PDL of IEEE 1687

Key Features

+ Analyze RTL design or netlist to identify memories
+ Plan MBIST engines
+ Insert into RTL design or netlist / Top level hookup to JTAG
+ Verify stand-alone/ Verify partition level / Verify top level
+ Automated subchip integration flow
+ Fully supported P1500 interface and Tap controller
+ Generate test patterns and SVF file
+ Incremental repair capability / Programmable March-style algorithm
+ APB interface for BIST test and fuse operation
+ Diagnosis test, Characterization test and SVF debug flow

Applications

Communications, Data Processing, Industrial, Automotive

Deliverables

Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
Synthesis and STA scripts
User guide documents
SV/UVM Verification suite with BFM

Technical Specifications

Maturity

Available

Availability

Yes

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