A bridge to convert the slave SPI interface to the master I2C interface and vice versa
Overview
The dti_spi_to_i2c is a bridge to convert the slave SPI interface to the master I2C interface and vice versa.
Key Features
- SPI clocking modes 0, 1, 2, and 3 are supported
- Programmable Clock polarity and phase (CPOL and CPHA)
- Transfer data bit MSB first
- I2C-bus slave interface operating up to 400 kHz
- Uses 7-bit slave addressing
- Use separated Async. FIFO for Transmitting and Receiving Data, with programmable user-specified on runtime-changeable levels
- Programmable Clock Divider for I2C Master
Benefits
- Compliant with the following specifications: AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
Applications
- Communications, Data Processing, Industrial, Automotive
Deliverables
- Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- Synthesis and STA scripts
- User guide documents
- SV/UVM Verification suite with BFM
Technical Specifications
Maturity
Pre Silicon
Availability
Yes
Related IPs
- A bridge to convert the slave SPI interface to the master UART interface and vice versa
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- I2C Controller IP – Slave, Parameterized FIFO, APB Master Interface (I2C2APB)
- I2C Controller IP – Slave, Parameterized FIFO, AXI Master Interface (I2C2AXI)
- I2C Controller IP – Slave, Parameterized FIFO, AHB Master Interface (I2C2AHB)
- I2C Bus Master / Slave Controller Interface with FIFO