The 40/100G Ethernet MAC & PCS + RS-FEC is a multi-rate IP core supporting 40G and 100G line rate. The core is designed using advanced design techniques leading to unmatched ultra-low gate count utilization and great latency performances. It includes a rich set of standard and advanced features making it ideal for a large number of applications.
The IP core can support full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.
The core includes Reed Solomon FEC RS(528, 514, 10) with FEC bypass and error correction bypass capabilities. Two other versions of the IP core are also available, each supporting a single rate, i.e. 40Gbps or 100Gbps (with RS-FEC).
40/100G Ethernet MAC and PCS + RS-FEC
Overview
Key Features
- MAC FEATURES
- Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average
- Programmable IPG length
- Programmable Maximum Receive Unit (MRU), Maximum Transmission Unit
- User facing logic interface 256-bit @ ~402.8MHz
- Ethernet flow control and congestion management using pause frames with programmable quanta
- Programmable Tx minimum packet length with enable/disable padding option
- Programmable Rx minimum packet length
- Tx Frame Check Sequence (FCS) computation and insertion
- Programmable Tx FCS pass-through and corruption insertion modes
- Programmable keep/strip Rx FCS
- Programmable Rx FCS error detection and marking
- Programmable Tx and Rx large frame threshold detection
- Programmable Tx and Rx path VLAN detection (Programmable TPID, stacked VLAN)
- Programmable Rx frame discard & marking
- Configurable statistics vector and collector on transmit and receive MAC data
- PCS FEATURES
- Supports 40GBASE-R and 100GBASE-R PHY based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes
- Supports block synchronization and BER monitor
- Supports multiple lanes swapping, lane alignment and deskew
- Configurable statistics vector and collector on transmit and receive PCS
- RS-FEC FEATURES
- Built-In Reed Solomon FEC RS(528, 514, 10) with FEC bypass and error correction bypass capabilities
- Statistics information for RS-FEC decoder (FEC align status, corrected & uncorrected FEC codewords
Benefits
- Industry leading performances
- Ultra-low gate count
- Ultra-low latency
- Ease of use
- Flexibility & scalability
- Supports wide range of FPGA devices
- High timing margin
Block Diagram
Applications
- Data Centers
- Smart NIC
- Low-Latency Switches
- QoS-Based Packet Processing
- Test and Monitoring Equipment
- Backhaul Solution
- Video over IP
Deliverables
- Datasheet & user guide
- Encrypted Verilog
- Constraints file
- Reference design
- Technical support
- Optional IP design customization