3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process
Overview
3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process
Technical Specifications
Foundry, Node
UMC 40nm
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process
- 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process
- MIPI DPHY v1.2 RX 2 Lanes - SS 8LPU 1.8V, North/South Poly Orientation for Automotive ASIL B Random, AEC-Q100 Grade 1
- MIPI DPHY Rx 4 Lanes - UMC 22ULP 1.8V, North/South Poly Orientation
- MIPI DPHY Rx 2 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
- MIPI DPHY v1.2 RX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation