16550D High Speed UART IP core - Universal Aysynchronous Receive/Transmit

Overview

Arasan 16550D High Speed UART IP core is a 16550-compliant Universal Asynchronous Receiver/Transmitter (UART) with FIFO or expanded FIFO.

The UART performs serial to parallel conversion of data received from the serial interface, and parallel to serial conversion of data received from the CPU interface. Both character and FIFO modes are supported.

The 16550D High Speed UART IP core is an RTL design in Verilog and VHDL that implements an UART on an ASIC, or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications.

Arasan 16550D High Speed UART IP core has been widely used in different applications by major chip vendors.

Key Features

Complies with UART 16550D specification
Complies with SD_PHS Specification Ver1.0
Supports character mode, FIFO mode, and extended FIFO mode
Programmable Serial Interface Characteristics :

5,6,7,8 bit characters
Even, odd parity bit generation and detection.
1, 1 1/2, 2 Stop bit generation.

Independently controlled Receive, Transmit, Line Status Interrupts.
Programmable Baud Generator divides any clock input by 1 to 65535 and generates the clock * 16.
Line Break Generation and Detection.
MODEM Control Functions. (CTS, RTS, DSR, DTR, RI and DCD ).
Loop Back Checking.
Independent Receiver clock Input.
Complete status reporting

Benefits

Fully compliant core with proven silicon
Premier direct support from Arasan IP core designers
Easy-to-use industry standard test environment
Unencrypted source code allows easy implementation
Customer training available
Reuse Methodology Manual guidelines (RMM) compliant Verilog code ensured using Spyglass

Deliverables

Verilog RTL
Synthesis and Test Scripts
Test Bench
Documentation
Behavioral models
Software drivers
Evaluation board

Technical Specifications

Maturity

Silicon proven

Availability

now

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