The NOEL3 is a configurable RISC-V processor IP core, described in VHDL. The architecture is designed to utilize a small area footprint and to maintain execution predictability.
Configurable RISC-V processor IP core
Overview
Key Features
- 32-bit RISC-V processor – with configurable extensions
- RV32I: integer essential instructions
- M: integer multiplication and division
- A: atomic instructions for concurrency
- F: single-precision floating-point arithmetic
- C: compressed instructions to reduce code size
- B: bit manipulation instructions
- Zfh: half-precision floating-point operations.
- Zfa: additional floating-point instructions
- Debug module
- Deterministic execution time guaranteed by barrel processor architecture
- Configurable number of hardware execution threads (2 to 7)
- One thread is always reserved for SoC operations
- Utilizes tightly coupled memories instead of caches for predictable memory access
- RISC-V PLIC interrupt controller
- Support of AMBA AHB and APB-like deterministic bus for external memory and peripherals
- Companion IP cores for bus fabrics, peripherals, networking and security (GRLIB IP Library)
Block Diagram
Technical Specifications
Short description
Configurable RISC-V processor IP core
Vendor
Vendor Name