12-bit 2-channel 50 to 125 MSPS pipeline ADC
Overview
055TSMC_ADC_03 is a low power 2-channel 12-bit ADC based on a high-performance pipelined architecture. The block consists of 2 ADC cores, a clock signal generation circuit, an output code generation circuit and a reference voltage source. Separate power supply of the analog and digital circuits is implemented. The ADC settings allow to switch the block (or one of the channels) to standby mode.
Key Features
- TSMC CMOS 55 nm
- Resolution 12-bit
- Conversion rate from 50 to 125 MSPS
- Different power supplies for digital (1.2 V) and analog (1.2 V) parts
- Differential full-scale input range peak-to-peak 1 V
Applications
- Transceiver systems
- Optical networking
- Telecommunication systems
- Mobile communications
- Measurement equipment
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC CMOS 55 nm
Maturity
silicon proven
Availability
Now
TSMC
Silicon Proven:
55nm
FL