10GBase-KR Ethernet Verification IP

Overview

The 10GBase-KR Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface 10GBase-KR. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. XGMII TBI verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.

10GBase-KR Ethernet Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

10GBase-KR Ethernet Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Follows 10GBase-KR specification as defined in IEEE 802.3
Supports scrambler
Supports FEC
Supports backplane auto-negotation
Supports CDR for serial protocols
Supports MDIO slave and master model as per Clause 22 and Clause 45
Supports Glitch insertion and detection
Supports Pause frame generation and detection.
Supports all types of 10GBase-KR TX and RX errors insertion/detection.
- Oversize, undersize, inrange, out of range Packet size errors
- Missing SPD/EPD/SFD framing errors
- SFD on wrong lane
- CRC Error
- Lane skew insertion
- Disparity error injection
- Invalid /D/ and /K/ character injection
- Variable preamble and IPG insertion
- Invalid block code insertion
- Sync bit corruption
- FEC error injection
- Scrambler error injection
Comes with 10GBase-KR Tx BFM, 10GBase-KR Rx BFM, and 10GBase-KR PCS Monitor
Monitor supports detection of all protocol violations.
Built in coverage analysis.

Benefits

Faster testbench development and more complete verification of 10GBase-KR designs.
Easy to use command interface simplifies testbench control and configuration of 10GBase-KR TX and RX.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite (UNH) containing all the testcases.
Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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