10G 64b/66b WIS Ethernet Verification IP

Overview

The 10G 64b/66b WIS Ethernet Verification IP is compliant with IEEE 802.3ae specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface 64b/66b WIS. It can work with Verilog HDL environment and works with all Verilog simulators that support SystemVerilog.

10G 64b/66b WIS Ethernet Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

10G 64b/66b WIS Ethernet Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Follows 10G specification as defined in IEEE 802.3ae.
Supports all types of 64b/66b WIS TX and RX errors insertion/detection.
Comes with 64b/66b WIS Tx BFM, 64b/66b WIS Rx BFM, and 64b/66b WIS Monitor
Monitor supports detection of all protocol violations.
Supports Pause frame generation and detection.
Built in coverage analysis.

Benefits

Faster testbench development and more complete verification of 10G 64b/66b designs.
Easy to use command interface simplifies testbench control and configuration of 10G 64b/66b TX and RX.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite (UNH) containing all the 10G 64b/66b testcases.
Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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