10G-100G MACsec Security Module for Ethernet
Overview
The Synopsys 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 specification. The IP provides a complete set of features that enable the user to define an optimized MAC in products across a range of 100G/200G/400G/800G applications. The Synopsys IP passes received MAC frames without modification to the user application or to the Ethernet line. In addition, the IP supports IEEE-managed objects, IETF MIB-II and RMON for management applications (e.g., SNMP). On the application side, the Synopsys 100G/200G/400G/800G Ethernet MAC IP implements a flexible FIFO interface that can be connected to a user application. On the Ethernet line side, the IP implements a 1024-bit CDMII (800G Media Independent Interface) to connect to an 800G PCS. When operating in 200G/400G or 400G speeds, the IP implements a 512-bit CDMII to connect to a 200G/400G PCS. The 100G Ethernet MAC IP implements a wide CGMII/XLGMII (100G/40G Medium Independent Interface) that supports a 10G operation. Synopsys’ 100G/200G/400G/800G Ethernet MAC IP seamlessly interoperates with Synopsys 100G/200G/400G/800G Ethernet PCS IP and Synopsys 112G Ethernet PHY IP to provide a complete Ethernet MAC, PCS and PHY solution for 100G/200G/400G/800G systems.
Key Features
- Full MAC layer and reconciliation sublayer implementation compliant with the IEEE 802.3 specification
- Standard preamble and Start of Frame Delimiter (SFD) insertion and deletion
- Lane, data alignment, PHY error and local/remote fault signaling handled by the reconciliation sublayer
- CRC-32 checking with optional forwarding of the FCS field to the user application
- CRC-32 generation and append on transmit or forwarding of user application provides FCS selectable on a per-frame basis
- Pause frame generation by dedicated command pin with programmable Quanta
- Programmable and maximum length supports any frame up to 32K (e.g., jumbo frame or any tagged frame)
- Supports VLAN tagged frames according to IEEE 802.1Q and double VLAN tags (Stacked VLANs)
- Supports IEEE1588 applications providing receive and transmit timestamps with additional transmit timestamp storage and interrupt, and 1-step frame update
- Deficit Idle Counter (DIC) for optimized performance with minimum IPG; supports non-standard short preambles
- Clock and data rate decoupling with programmable asynchronous FIFOs
- Programmable Clause 22 and Clause 45 MDIO primary interface for PHY device configuration and management
- Optional Ethernet pause frame (802.3 Annex 31A) termination providing fully automated flow control without any user application overhead
- Optional AXI4S support in Synopsys 800G & 400G Ethernet IP and AXI4 in Synopsys 100G Ethernet IP
- Optional Priority Flow Control (PFC) frame support with 8 classes for higher layer congestion management; the 100G IP supports 16 classes via a synthesis parameter
- Optional 802.3 basic and mandatory managed objects statistic counters and IETF Management Information Database (MIB) package (RFC2665) and Remote Network Monitoring (RMON) counters
Benefits
- Supports all required features of the IEEE 802.3bs specification
- Supports IEEE-managed objects, IETF MIB-II and RMON for management applications
- Application interface includes the Synopsys native interface 512-bit or 1024- bit FIFO for more than 200G operation
- Designed to be used with Synopsys 100G/200G/400G/800G Ethernet PCS IP
- Supports IEEE 1588 applications
- Silicon-proven
Applications
- High-Performance Networking
- High-Performance Computing
Deliverables
- SystemVerilog RTL Source code
- Verilog Testbench environment with example testcases
- Scripts and constraints files for implementation tools like Spyglass Lint/CDC, DesignCompiler, etc.
- IPXACT views for register maps
- Documentation: Databook, Integration User guide and Release Notes
Technical Specifications
Maturity
Available on request
Availability
Available