Verify Smarter, Not Harder
By Mark Olen, Mentor, a Siemens Business
EETimes (April 1, 2019)
Process technology and verification enjoy a circular and mutually beneficial symbiotic relationship. Improvements in functional verification tools make technology adoption economically viable, and technology advances spawn more complex designs, which demand an increase in sophisticated verification.
Process technology and verification enjoy a circular and mutually beneficial symbiotic relationship. Improvements in functional verification tools make technology adoption economically viable, and technology advances spawn more complex designs, which demand an increase in sophisticated verification.
To keep up with the rapid pace of innovation and rising design and verification complexity, engineering teams need to verify smarter, not harder. New and reimagined technologies and methodologies — including portable stimulus, coverage, and power-aware verification — give them the tools to do so.
Functional verification is the science of validating a representation of a particular chip design targeted for a given technology. This validation must be of a sufficient accuracy and rigor to make the end product economically viable. It can do so by maximizing the likelihood of high-quality, first-silicon working in the end application with the greatest possible number of scenario variants.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Articles
- SoC Test and Verification -> How to verify ADSL chips
- SoCs: DSP World, Cores -> New DSP architectures work harder
- SoC not high enough on agenda for mass market
- Analog IP business not likely soon, say DAC panelists
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events