What Goes Around Comes Around: Moore's Law At 10nm And Beyond
Greg Yeric, ARM
Semiconductor Engineering (February 13th, 2014)
With lithography scaling on hold and the silicon MOSFET losing its 40-odd-year grip on scalability, how can the industry continue to squeeze scaling?
Gordon Moore penned his famous observation in an era when the people developing the process were also the people designing the circuits. Over time, things got more complicated and work specialization set in, but all was well in the world for many years as the fabs kept delivering on Moore’s Law. Yes, designers had to come up with lots of tricks to advance power and performance scaling, but that’s Dennard’s problem, not Moore’s. As a designer in the present day, if you view Moore’s Law from that original, unilateral perspective, then Moore’s Law is indeed long gone.
Or at least on an extended vacation.
Lithography scaling is on hold and the silicon MOSFET is losing its 40-odd-year grip on scalability. I’d like to use this forum to provide a few observations along these lines, which fall into two categories: (1) squeezing existing technology harder and (2) path-finding to the best solution in an increasingly complicated set of technology scaling options.
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond
- CFET Beyond 3 nm: SRAM Reliability under Design-Time and Run-Time Variability
- Embedded Systems: Programmable Logic -> Embarrassment of riches hinders proper use of Moore's Law
- Embedded Systems: Programmable Logic -> Adaptive tech extends Moore's Law
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design