Deriving design margins for successful timing closure
Ateet Mishra, Amol Agarwal, and Abhishek Mahajan (Freescale)
EDN (August 13, 2013)
With the fast developing technology, the complexity of design is increasing day by day. To meet lower technology challenges and to achieve good silicon yield, SOC design flows have been enhanced and have introduced more number of design implementations steps. With every implementation step which takes design towards realistic working silicon, SOC design timing performance degrades due to various factors which were not apparent at previous implementation step. Thus it is very important to have a right estimate of design frequency since first stage of design implementation. The important parameter which makes it possible are called Design Margins.
Design margins
Design Margins are the extra pessimism introduced in terms of design uncertainty which covers the expected timing hit of every stage in implementation cycle so as to achieve targeted frequencies well in time. It is very much required to have a right estimate of design margins.
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions
- Timing Closure on FPGAs
- Latches and timing closure: a mixed bag
- Design Rule Violation fixing in timing closure
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design