Vertical Solution for PCI Express

    
Abstract:

The electronics industry has been quick to embrace the concept of IP Reuse, indeed the rapid growth in the use of Semiconductor IP (SIP) is generally expected to continue throughout this first decade of the new millennium. Much of the debate around IP Reuse is focused on quality issues and potential weaknesses in IP vendor business models. Cadence has developed a Vertical Solutions approach which not only deals with these issues but also extends the reuse model to increase customer productivity throughout the full development process.

The Vertical Solution for PCI Express brings together soft and hard SIP with Verification IP, Emulation solutions, Silicon Design-in kits for   board design and protocol analysis tools for debug and compliance testing. These are augmented with Engineering Services – which provides PCI Express expertise wherever it is needed throughout the development and verification process.

The Vertical Solution has been developed in collaboration with market leaders such as Rambus, Denali and Catalyst. To provide more customers with access to best in breed tools and IP we will increase the portfolio of Vertical Solutions to support technologies such as Ethernet and USB. To facilitate this we have developed the OpenChoice IP partner program which audits IP and suppliers so as to select vendors who offer the best range of quality IP, backed up with world class support.

This paper describes the benefits provided by Vertical Solutions in developing new products which integrate complex new technologies. It discusses the challenges of implementing high speed interconnects such as PCI Express as well as the business issues faced by companies looking to find quality IP from dependable suppliers. In particular the paper highlights how the Vertical Solution for PCI Express provides an excellent model for maximizing the effectiveness of IP, EDA tools and Engineering Services.

New Technology – New Challenges

The arguments for moving to high speed serial interconnects have been made. The options such as PCI Express, RapidIO and HyperTransport have been considered. It is time to make product, to do so quickly and for the majority of developers to do so using PCI Express.

For companies looking to move from legacy PCI to PCI Express the significant benefits that they receive in terms of bandwidth and scalability come at the price of considerable technical challenge

• complex, high speed digital and analog design
• verification from block simulation through to silicon compliance
• multi-gigahertz package and board design and analysis

Added to these are business challenges – with PCI Express being targeted at fast moving and often low margin markets in which products require regular feature updates. The need to increase productivity is critical. The way to succeed is to optimize reuse whenever and wherever possible.

What is a Vertical Solution?

PCI Express product development is a complex multi-stage process. At each stage there is opportunity to increase productivity through the prudent use of IP, tools and services. In the past developers have been forced to rely on point solutions – hoping that the benefits of reuse would compensate for the difficulties encountered in working with a variety of unrelated suppliers.

The Vertical Solution approach is focussed on combining point solutions into an offering in which the constituent parts have been integrated and tested together.
 

Figure 1 Vertical Solution for PCI Express

The diagram above illustrates the comprehensive nature of the Cadence Vertical Solution for PCI Express.

On the left hand side we see the Cadence platforms which enable companies to design and verify complex and high speed analog and digital circuits and carry out board and package design and analysis.

The right hand side of the diagram lists the enabling technologies which help developers to reduce risk and accelerate schedules

• Design IP which can be tailored to the customers exact requirements: flexible soft IP combined with area and power efficient SerDes from Rambus
• Verification IP from Denali which enables compliance and compatibility testing
• In Circuit Emulation enabling developers to test at speed using real traffic as well as hardware and software co-design
• Silicon design-in kits which accelerate the design of multi-giga hertz PCBs
• Protocol Analyzer / Exerciser tools from Catalyst which accelerate silicon debug and enable compliance preparation

To complete the picture Engineering Services are shown on the extreme right of the diagram. This is a critical aspect of the Vertical Solutions approach – when developers lack specific resources we can provide them with access to engineering teams who have deep understanding both of our solutions and of PCI Express.  So, for example, if we provide Engineering Services to assist a customer to develop their verification methodology then we do so from the position of expertise in verification and in PCI Express.

There are many reasons why Cadence decided that the Vertical Solutions approach is a great way for us to provide our customers with additional value-add,   and these are described in detail over the following sections. However there are a couple of points which are worth emphasizing:

Firstly wherever possible we ensure that our solutions talk to each other. For example when developers want to integrate Cadence soft IP with Rambus hard IP and test it using Denali verification IP – they know that we have already integrated these cores together and tested them. In so doing we ensure that here’s not going to be any surprises. The cores talk to each other and are seamlessly integrated into the tools. It’s not just reuse - it’s fast and reliable reuse.

Secondly we focus on looking for ways to increase our customers’ productivity. If our Engineering Services teams find and use great tools then we work with the supplier to add them to the Vertical Solution, helping our customers to benefit from our experience and providing them with best access to these tools.

IP – hero or villain

Ask a group of SoC developers to raise their hands if they have used IP and the chances are that every hand will be raised. Ask those who have never had major problems with integrating IP to drop their hands and every hand will still be raised. Arguably the benefits of using IP outweighed the pain – but we need to find ways to significantly reduce or completely remove the pain.

The Vertical Solutions approach presents developers with IP from suppliers who demonstrate the best balance of portfolio, infrastructure and all round support – and ensures that the IP has been used on Cadence tools.

Cadence has an IP Partner Program, OpenChoice, which provides the required infrastructure to source and audit IP and make this available for Cadence customers. OpenChoice makes use of the Cadence Compliance Kit which is based on the Quality IP (QIP) Metric from the Virtual Sockets Interface Alliance (VSIA). This helps to accelerate auditing the quality of IP suppliers and their products – ensuring that adequate delivery and support infrastructure is in place and that the quality of deliverables matches customer requirements.

By working through the Compliance Kit and actively engaging with potential IP partners we ensure that we select companies who have genuine credibility as long term IP providers.

Having identified IP of interest for the Vertical Solution we then integrate cores together and test these on Cadence platforms.

With PCI Express, for example, there is a requirement to source both a digital controller and SerDes IP – so we integrate these in a single design and simulate them together. Combining multiple cores can be a frustrating business, bad enough when the cores are from a single supplier – but when the cores come from different suppliers the opportunity for misunderstanding and delay increases substantially.

By ensuring that this work has been done before our customers use the cores we ensure that they can benefit from reuse instead of being bogged down in unnecessary delay.

For our PCI Express soft and hard IP cores we are progressing from the simulation of interoperability to hardware based compliance and interoperability testing at PCI SIG Compliance Workshops. The value of taking not just the digital controller, or the SerDes alone, but the combined cores to compliance testing cannot be overstated. By selecting a digital controller and SerDes which have been through compliance together you move from purchasing IP to purchasing a solution.

In a similar fashion there can be many sources of potential issues associated with integrating design IP with verification IP. To maximize the benefits of reuse you need verification IP that can be readily integrated into the verification environment of your design. There will be even greater reduction of risk and increased productivity if the combined verification environment has been proven on your EDA platform.

The problems found while integrating verification IP into the verification environment of your design are often, although not always, minor. Examples include differences in signal naming standards, bit ordering problems and port width mismatches. However these can be seriously frustrating, and lead to significant time waste.

In order to maximize the value of using VIP as part of our Vertical Solution we have integrated the PureSpecTM VIP from Denali into the verification environment of our PCI Express IP digital controller cores.

PureSpecTM operates in active and passive modes. We provide one verification environment which supports PureSpecTM in active mode – whereby the VIP behaves as a Root Complex device driving the Cadence soft IP Endpoint. Likewise we provide a second verification environment which supports PureSpecTM in passive mode – whereby the VIP monitors the PCI Express bus during simulation with Cadence’s complete testbench and highlights any deviations from the specification.

We support customers in their use of Verification IP as a direct response to a growing market requirement to supplement testbenches which have been traditionally shipped with design IP. Quality testbenches are extremely useful in core verification and can often be modified for reuse on the top level design. However they fall short of enabling developers to implement a truly reusable verification strategy. VIP such as PureSpecTM provides access to system verification during the development phase and supports the creation of a reusable environment that can handle critical design changes.

PureSpecTM is particularly useful in that it provides a compliance suite that highlights violations by making direct reference to specific lines in the PCI Express specification. In addition it can drive and monitor the device under verification from different layers, a highly flexible feature for many developers.

By providing soft and hard IP cores which are proven to work together and integrating these with Verification IP the Vertical Solution makes both the selection and the use of IP a positive and productive experience.

Emulation

For many companies Emulation has become a requirement. Increased device complexity and schedule pressure means that developers need to get their product right first time and, whenever possible, to accelerate product development schedules through enabling hardware / software co-design.

One of the first questions which needs to be answered for new technology development is how the design will map into available emulation platforms. In particular will the design be synthesizable to FPGA, both from a speed and a gate count perspective.

FPGA based emulation can be highly effective – not only by enabling real-time test using real traffic and by enabling early software development but also by  enabling the development of a platform suitable for  compliance workshop testing. There are many potential pitfalls at compliance workshops, not least last minute spec changes common to new standards. Being able to make changes to an FPGA based design provides the ability to react to these changes, and can be the difference between passing at one event or having to wait until the next.

PCI Express presents some interesting challenges for FPGA evaluation – particularly with respect to support for multiple lanes. It’s fairly straightforward to synthesize and time a single lane solution to FPGA. However 4 lane solutions are more of a challenge and 8 lane solutions extremely difficult. FPGA emulation requirements are something which developers need to discuss with their IP suppliers up front. Cadence has specific cores which have been targeted to support the growing demand for FPGA based emulation.

For developers looking to emulate complex systems, or to get to emulation quickly using a proven platform, emulation on the massively powerful Palladium platform from Cadence is a tried and tested solution. With in-circuit emulation on the Palladium, the design is synthesized to the accelerator and interfaced to the outside world using a rate-matching card known as a SpeedBridge.


Figure 2 SpeedBridge: data buffering and rate matching between DUV and outside world

In addition, as was the case during the early stages of PCI Express evolution, it is possible to design a SpeedBridge that will enable testing of new technologies before systems supporting these technologies become available.

Accelerating Design-in

Successful product companies need to ensure that their customers progress through the prototyping phase and on to volume production as quickly as possible. Many companies do a great job of developing and proving products but suffer financial hardship waiting for customers to get to volume production.

High-speed System-on-Chip (SoC) ICs are challenging to implement in a system of PCBs. The availability of new types of packages that condense 1000s of pins into a very small area makes the challenge even greater.

Silicon Design-in Kits are reference design kits provided by IC vendors that show at least one way to implement their IC product.  These kits include pre-configured and correlated simulation models, along with schematics and layouts that illustrate proper connectivity.  Trying to communicate proper design technique in a paper document is unwieldy, particularly with the possibility of language and communication problems.  In the case of a pre-tested Silicon Design-in Kit, a picture is truly worth a thousand words.

An added challenge for PCI Express applications is that there are many board designers who are practiced in the development of relatively slow legacy PCI products who are now faced with designing multi-gigahertz (MGH) transceivers onto their PCB.

The simulation of MGH transceivers creates new issues for developers who have traditionally focused on transistor level simulations using spice models. While the accuracy of spice models is undisputed, simulation at transistor level is very slow.  Accurate MGH transceiver performance requires simulation of many thousands of bit patterns – as the transceiver eye gradually and marginally closes with the simulation of more and more patterns. Cadence Silicon Design-in Kits make use of MacroModels which accurately represent the behavior of MGH transceivers but which simulate hundreds of times faster. Simulations are shown to be accurate through correlation to SPICE simulation results.

Transceiver MacroModels enable board designers to carry out what-if analysis by enabling the running of large numbers of board simulations in a reasonable time-frame.
Silicon Design-in Kits for PCI Express enable board designers to be up and running, viewing waveforms, within minutes of installation. They provide an excellent example of how reuse adds significant value for customers, particularly when optimized for use with EDA tools.

Debug and Compliance

The most recent addition to the Vertical Solution for PCI Express is Protocol Test and Analysis Tools from Catalyst. The solution consists of a Development Platform along with Analyzer / Exerciser boards - the Analyzer monitors the PCI Express bus looking for protocol errors and the Exerciser emulates upstream or downstream traffic.

During early debug the system under test can be brought up gradually as the Exerciser drives the PCI Express bus. As debug progresses and the system under test becomes capable of driving and responding to the bus, the Analyzer is used to observe bus operation.

Cadence Engineering Services teams have used Catalyst tools during prototype debug and in preparation for compliance test – and found them to add significant value.

The Analyzer board triggers on select PCI Express events, with the bus contents being pre-filtered before and then displayed in an easily read format which translates serial activity to viewable packets.

The Exerciser captures both what it sends and what it monitors on the bus. Again triggering and filtering are employed in viewing the PCI Express bus signals. In addition to API and GUI control options the Exerciser mode supports a compliance option which enables devices to be compliance checked.
 

Figure 3 PCI Express Compliance Suite

As you can see this provides a clear and easy to use interface – with simple controls and regularly updated descriptions of the tests. The compliance test suite provides a written summary of the system under test’s performance – which is excellent preparation for participation at compliance workshops.

Conclusion

The Vertical Solutions approach is focused on maximizing the effectiveness of tools, IP and services. It improves productivity through improving access to quality solutions and ensuring that these solutions work seamlessly together.

PCI Express is an excellent example of where the Vertical Solutions approach can save developers enormous time and enable IC developers and their customers to be first to volume. It demonstrates the value of creating an aligned approach to the delivery of technology focused solutions.
Cadence is working with partners including Rambus and Denali to develop a further Vertical Solutions for technologies which are critical to our customers. These will include Gigabit Ethernet and USB 2.0.

Vertical Solutions are customer focused – directed by customer technology requirements, and driven by customer success.