Targeting SoC address decoder faults using functional patterns
Aashish Mittal, Glenn Carson, and Nitin Goel, Freescale Semiconductor
embedded.com (September 28, 2014)
Even though you have thoroughly verified your SoC design during the development cycle, sometimes critical faults during manufacturing can lead to failure in the field, one of the most serious of which is the address decoder stuck-at fault [1]. This is a critical fault that must be tested for on each and every piece of silicon that needs to pass qualification for an industry standard [2].
Testing of RAM and other memories come under the scope of Design for Test (DFT). It is generally achieved by implementing a number of algorithms which are either part of MBIST (memory built-in self test) delivered by a third party or DFT patterns targeted for particular faults in memory [3]. Conventionally, no special fault detection technique is used for an address decoder as they are assumed to be covered with array testing. Some of earlier MBIST controllers do not support Algos for checking ASOF faults, so our approach is to use a functional tester pattern to catch these faults on silicon.
To read the full article, click here
Related Semiconductor IP
- Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
- PUF FPGA-Xilinx Premium with key wrap
- ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- ASIL-B Ready PUF Hardware Base
- PUF Software Premium with key wrap and certification support
Related White Papers
- Using multi-bit flip-flop custom cells to achieve better SoC design efficiency
- Bug hunting SoC designs to achieve full functional coverage closure
- An Efficient Device for Forward Collision Warning Using Low Cost Stereo Camera & Embedded SoC
- A cost-effective and highly productive Framework for IP Integration in SoC using pre-defined language sensitive Editors (LSE) templates and effectively using System Verilog Interfaces
Latest White Papers
- Boosting RISC-V SoC performance for AI and ML applications
- e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
- How to design secure SoCs, Part II: Key Management
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU