Optimizing DSP functions in advanced FPGA architectures

Although FFT and FIR filters may seem complex, in reality they use simple add/subtract/multiply operations. So how can these arithmetic modules, along with shift and pipeline registers in modern FPGAs, be configured in different modes to provide greater flexibility and control with desirable levels of performance? In this "How To" paper, we outline practical steps, along with common mistakes to avoid, for successfully extracting optimal results in your DSP-based FPGA designs.

In high-performance, FPGA-based DSP designs, which typically demand high bandwidth, high throughput, and low operating power, there is very little room for error during the design-planning process. In order to be successful when tackling such designs, you need to understand certain nuances about design specifications and target technology architectures, as well as synthesis tools. With the realization that it is difficult to be an absolute expert on every possible aspect of DSP-based design using programmable logic devices, this article outlines some actions you can take to meet your ultimate objectives when handling these designs.

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