Virtual testing with model-based design
industrialcontroldesignline.com (August 17, 2009)
Virtual testing, based on system simulation and Model-Based Design, takes the traditional "test-at-the-end" system development process (represented in the V diagram) and makes it more iterative. Virtual testing shortens both the design cycle and the final physical testing phase.
The Problems: System Complexity and Late-Stage Error Detection
Complexity in embedded software development is driving the cost of test and verification to as much as 70% of overall development costs. Industrial automation, automotive, and aerospace engineers conduct exhaustive design and code reviews and build increasingly complex test systems to confirm that the software in embedded processors meets high-integrity standards and design requirements. And as verification consumes more time, engineers have fewer opportunities to innovate and create product differentiation through design optimization.
Many organizations are finding that most errors they uncover in test and integration were introduced at the beginning of the design process while interpreting system requirements. Engineers now face the challenge of checking for errors and "cleaning them out" closer to the beginning of the development process, when they are cheaper to fix.
Finally, as development teams grow and become geographically dispersed, they are seeking better ways to collaborate.
To read the full article, click here
Related Semiconductor IP
- Message filter
- SSL/TLS Offload Engine
- TCP/UDP Offload Engine
- JPEG-LS Encoder IP
- JPEG XS - Low-Latency Video
Related White Papers
- Dealing with automotive software complexity with virtual prototyping - Part 3: Embedded software testing
- Design & Verify Virtual Platform with reusable TLM 2.0
- Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
- SoC Test and Verification -> Testing mixed-signal Bluetooth designs
Latest White Papers
- Memory Safety Features Impact on Ibex based processor area
- A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans
- Learning Cache Coherence Traffic for NoC Routing Design
- Generative AI for Analog Integrated Circuit Design: Methodologies and Applications
- HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction