FPGAs versus DSPs: Effective implementations of 3G basestations

FPGAs versus DSPs: Effective implementations of 3G basestations
By Paul Ekas, Senior Manager, DSP Group, Intellectual Property Business Unit, Altera Corp., San Jose, Calif., EE Times
November 8, 2002 (12:23 p.m. EST)
URL: http://www.eetimes.com/story/OEG20021107S0025

The evolution of 3G wireless network equipment is being driven both by business and technical issues. Trade-offs in cost, risk (upgrade ability), and time-to-market are factors in the development of the various pieces of equipment in a 3G network, the radio network controller (RNC), the mobile switching center (MSC), and the basestation (BTS).

On the technical side, there is a convergence of very high performance dedicated processing including packet and digital signal processing, complex control software, and LVDS based switched backplane interconnect technology. Designers have been addressing these issues by using architectures based largely on programmable hardware (FPGAs) and software components (processors), but they face the dilemma of whether to migrate to ASICs to minimize costs. However, this no longer needs to be the case given the rapid evolution in FPGAs and DSPs.

The BTS is an interesting example of this dilemma as it experiences the highest rate of evolution (requirement for flexibility) and represents the highest volume (requirement for low cost) of the three pieces of equipment used in 3G networks. Most leading basestation architectures use DSPs and FPGAs to address the flexibility requirements driven by the rapid evolution of standards and advanced signal processing techniques. All leading BTS manufacturers, however, have invested in ASICs for much of this processing in an attempt to reduce costs.

Key areas where changing standards are impacting the hardware architectures are in the adoption of HSDPA in Release 5 of 3GPP and 1xEVDO and 1xEVDV in 3GPP2. Essentially, 3GPP and 3GPP2 are the standards bodies in charge of WCDMA and CDMA 2000 evolutions, respectively. These evolutions add new modulation and aggregation techniques to the uplink and downlink communication channels. All of these evolutions require changes in the hardware architectures that preclude the use of fixed ASICs that cannot be reprogramm ed to meet the demands of enhanced communication standards. As a result, vendors who are using DSPs and FPGAs in their production equipment are well positioned to deliver these enhancements to service providers ahead of vendors relying on ASIC technology.

But even with the evolution of standards to support higher data rates and more users, there is demand to significantly increase the radio performance in a given spectrum. Signal processing algorithms — currently under development and known as multi-user detection and adaptive beam forming — require increases in signal processing that can be ten to one hundred times more difficult than the baseline standard implementations.

Within all these standards and advanced signal processing techniques, there is a complex mix of control and dataflow processing. The dataflow processing is very hardware intensive and is well suited to dedicated programmable hardware solutions. There is greater complexity in the control processing. D epending on the particular control algorithm being implemented, it may be better suited for implementation using either hardware state machines or software on a control processor.

The control processing that can be well described by state machines includes the hardware architecture control — for example where time-sharing is used — as well as fast reaction physical layer control. As the processing moves away from the antenna towards the backhaul of the system, the control has a greater impact on the dynamic resource utilization where strong dependencies exist on data rates and other system operational issues. This latter type of control is better suited for software-based processing. The dichotomy in the system has led to implementations based on FPGAs for the dataflow and fast control portions of the system, and programmable DSPs for the more complex control oriented processing. Thus, all the chip-rate processing and some symbol rate processing in the channel element card resides on the FPGA and the rest of the symbol rate processing and some layer 1 control resides on the DSP.

During the evolution from field trials to network deployment of 3G wireless infrastructure equipment, there have been rapid improvements made in the semiconductor components in terms of device architectures and process geometries. This has driven an evolution in FPGAs to include software programmable control processors and an analogous evolution in the DSP to include hardware acceleration.

The evolution of the channel element card architecture is expected to go from DSP/FPGA toward a DSP/ASIC solution, with the ASIC replacing the FPGA. But challenges in the market adoption of 3G technology, such as upgradability and cost, reveal the effectiveness of FPGA-based solutions. ASICs will need to overcome these challenges to successfully displace FPGAs in 3G architectures. Source:Altera

Early in 3G equipment development, of all the software running on the DSPs, the major processing load was the decoder processing (Viterbi and Turbo) in the uplink. In response to this, companies such as Texas Instruments have integrated custom hardware accelerators for Turbo co-processing and Viterbi co-processing to reduce the effective number of DSPs required from eight c6415 devices to a single c6416. DSPs have thus consumed the majority of the processing from the symbol rate processing through the layer 1 control software.

FPGAs have also evolved during this time to include LVDS I/O, hard MACs, distributed memory, and control processors as flexible components for the hardware architect. This enables very dense dataflow architectures with tightly coupled control processing that are well suited to 3G chip-rate and symbol-rate processing. Designers are now ab le to implement very advanced architectures with a mixture of data flow processing, state-machine control, and software programmable control. This can be done quickly, easily, and with very low risk.

The expected evolution of the channel element card architecture has been from DSP/FPGA towards a DSP/ASIC solution where the ASIC displaces the FPGA. However, there have been a number of challenges with the market adoption of 3G technology that exemplifies the attractiveness of FPGA-based solutions. ASICs need to overcome these challenges to successfully displace FPGAs in 3G architectures.

The first challenge is long-term upgrade ability of infrastructure equipment both for the manufacturer and the service provider who deploys the equipment. The ability to evolve and upgrade equipment both on the production line and after field deployment is already optimally served by FPGAs. This is where ASICs cause a negative impact on long-term product success.

ASICs can not be upgraded with software to meet the standards evolution nor do they include improved performance gained from field deployment experience. They also can not fix bugs that will invariably occur in systems as complex as 3G. The direct impact is that the equipment vendor may struggle with time-to-market issues when delivering enhanced feature requirements. The primary impact on the end user, the service provider, is that new features will often require hardware upgrades throughout their network. Network operators achieve huge operating advantages when upgrades can be made using software delivered automatically through the network to reprogram thousands of DSP/FPGA based basestations versus a requirement to drive a service technician to each site to install updated ASIC based hardware.

The second challenge that ASICs must overcome is cost. ASICs require very high volumes to drive down the unit cost of the devices. 3G equipment deployments are not providing the volumes required to leverage an ASIC cost structure. The cost structure for ASICs include:

• Mask costs exceeding one million dollars for 0.13micron technology

• Expensive design and verification cycles before tape-out (exceeds mask costs)

• Manufacturing test vector development

• Complex bring-up processes, particularly with leading interconnect technologies like RapidIO and Hypertransport

• Long-term commitments to ASIC evolution requirements (repeat above costs every two years)

The result is that in the low to medium volumes projected for wireless infrastructure equipment, FPGAs can closely match the unit costs of ASICs.

FPGAs can meet the cost structure of ASICs due to several technology trends. For example, FPGAs use the latest process technology well ahead of standard ASIC flows, thus providing significant cost and performance advantages for the FPGA. They are combining this process advantage with architectures focused on high performance signal processing . And now they contain dedicated DSP processing blocks, each delivering industry-leading throughput in combination with distributed memory architectures that can sustain huge system processing bandwidth.

In addition, just in case the volume of components shipped does begin to justify an ASIC, Altera's FPGA technology has one more cost reduction trick up its sleeve. Customer designs already mapped to an Altera FPGA can take advantage of the company's HardCopy program which creates a hard implementation of the customers FPGA design. No timing or package impacts exist, so customers can just keep on shipping equipment, with very aggressive cost structures.

The deployment of 3G networks are still in their infancy. Initial 3G equipment deployment has begun and new deployments will continue over the next 15 to 20 years. Equipment designed for long-term product lifecycles and low costs are well positioned for the ongoing technical and business challenges inherent in the wireless infrastructure market. The evolution of DSPs and FPGAs to meet the equipment challenges makes them the architecture of choice for baseband channel element processing, the heart of the 3G basestation.