Chiplet Strategy is Key to Addressing Compute Density Challenges
By Balaji Baktha, Ventana Micro Systems
EETimes (September 28, 2021)
Data center workloads are quickly evolving, demanding high compute density with varying mixes of compute, memory and IO capability. This is driving architectures that are moving away from a one-size-fits-all monolithic solution to disaggregated functions that can be independently scaled for specific applications.
It is imperative to adopt the latest process nodes to deliver the needed compute density. However, doing so with traditional monolithic SoCs presents an inherent disadvantage due to escalating costs and time to market challenges resulting in unfavorable economics. To address this dilemma, chiplet-based integration strategies are emerging where compute can benefit from the most advanced process nodes, while application-specific memory and IO integrations can reside on mature trailing process nodes.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related White Papers
- Programmable Logic Holds the Key to Addressing Device Obsolescence
- Reconfiguring Design -> Reconfigurability: Designer's key strategy
- Addressing the new challenges of ASIC/SoC prototyping with FPGAs
- Addressing MIPI M-PHY connectivity challenges for more efficient testing
Latest White Papers
- Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard