Analog circuits need more than just DFT methods

Analog circuits need more than just DFT methods
By Steve Kosier, Vice President, Engineering, PolarFab Inc., Bloomington, Minn., EE Times
March 3, 2003 (11:10 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030228S0051

Digital design is, of necessity, performed at a very high level of abstraction. When dealing with millions to hundreds of millions of transistors, working at the transistor level is completely impractical. Designers of digital chips focus on things such as design-for-test (DFT), logic verification and synthesis quality. They are concerned with area, power and timing constraints of the design, obtaining timing closure of the physical design, the quality of the intellectual-property blocks they are using and many other high-level issues. In most cases, a digital designer is unconcerned with transistor- or even circuit-level issues.

By contrast, analog design is performed at a very low level of abstraction, traditionally the transistor level. In addition to often handling unusual voltages and currents that require special consideration, analog designs are driven from schematics rather than high-level code, and highly dependent on the quality of the simulation models.

The most important part of the analog EDA flow is the accuracy of the device models (both active and passive devices) and the inclusion of all relevant junction parasitics. This is understandable, given that many analog circuits, such as current mirrors and amplifiers, depend upon both the I-V curves and their derivatives. In digital circuits, by contrast, accurate I-V modeling is the primary concern.

For example, the parasitic pnp in an npn transistor or the parasitic npn in a double-tubbed lateral NMOS device can be turned on in an analog design's normal circuit operation in many types of power management circuits. Such things do not happen in digital circuits, except perhaps at the I/O pads. Hence, the circuit models must account for this behavior. Good analog models are typically implemented as subcircuits comprising a very accurate intrinsic transistor model surrounded by various additional parasitic devices.

The BSIM series of CMOS models is the most widel y used MOSFET models today. These public-domain models out of UC Berkeley are inherently scalable with well-established extraction and model-fitting algorithms. Scalable bipolar junction transistor (BJT) models are also very important for accurate analog designs, especially those done in purely bipolar processes. Since BJT models, such as the industry-standard Gummel-Poon model, are not scalable and extraction algorithms that support scalable BJT models are not generally available, providing fully scalable BJT models — as well as scalable resistors, capacitors, MOSFETs and lateral D-MOSFETs — are great enablers for analog designers.

The models must also account for process variation in an intelligent and usable fashion for the analog designer. All "process corners" or worst-case models must be tied to electrical-test parameters. These parameters have specifications and associated capability indices (Cpk) values, which can be readily understood by the designer. This link between the wafer fa brication facility and the models is crucial to designing analog circuits that will yield well over process variations.

Monte Carlo and mismatch modeling support are also necessary for some types of circuit optimization in analog design, compared with digital design, which uses nominal, slow and fast transistor model variations. Obtaining a reliable and meaningful coefficient for use in analog simulations is not a trivial task, but the benefits to the analog designer are very real.

Analog circuit simulation is generally performed with Spice or a Spice-like simulator in both the time and frequency domains. Some design automation can be obtained through scripting languages, but the design, still largely performed by hand, is done at the schematic level with the designer manually placing circuit elements and connecting them up as needed, running simulations and checking results.

Analog layout is often done by the chip designer, or by a layout specialist in close collaboration with the circuit designer. Experience has shown that a schematic-driven layout, complete with connectivity information, can speed up the layout process several-fold.

Some devices and structures in an analog design are invariably handcrafted at the polygon level. In addition, an analog process will have many device-specific layout rules and a very large device library. This places special requirements on design rule checking (DRC) and layout-vs.-schematic (LVS) code, because layer-to-layer rules will often depend upon factors such as whether the device is an npn, a high-voltage MOSFET, the upper plate of a poly-poly capacitor or some other specialized structure. DRC and LVS in digital designs, which typically use only CMOS transistors, run on huge databases, with no need to handle the many device-specific rules associated with analog designs.

Healthy EDA flow

Parasitic extraction and resimulation are a necessary step in a robust analog EDA flow, especially for high-speed designs or sen sitive feedback loops. It is important to extract both metal parasitics and underlying junction parasitics associated with the tubbing layers. The tubbing parasitics can significantly influence things such as power-supply rejection ratio, and hence must be accounted for in many analog designs.

Analog chips seldom use typical pad cells, which are supplied as standard with digital chips and are designed to be self-protecting against an electrostatic-discharge (ESD) event. The reason is simple: Analog chips are usually rather small and have unique I/O requirements, so using a digital-style pad cell would take up too much area and present too much loading or series resistance to the pad, or it might interfere with the intended function of the pin in some other way. Instead, ESD solutions often must be individually crafted for each pin in an analog design.

Most circuit designers are not ESD experts, however. ESD-related IP and consulting from the foundry are invaluable time-to-volume enablers for both the designer and the foundry. Through the use of ESD devices, ESD design manuals, ESD consulting and design reviews early in the design cycle, considerable success in first-pass ESD can be obtained regardless of process and product type.

Latchup, always a concern for integrated circuits, is particularly important for analog chips that drive large off-chip inductive loads. Such situations are prevalent in all switch-mode power supplies, motor drivers and many other power-management chips. Sophisticated guard ring techniques and floor planning can prevent latchup that would otherwise render a chip useless. By using guard ring rules, cells, structures and examples, and by consultations with the manufacturer, designers can achieve success in this area as well.

Analog CMOS and BiCMOS processes must have a digital standard-cell library for designers to use. The library need not be large, but must be area efficient, well documented and fully compatible with all popular synthesis, place and ro ute flows. Although smaller than the library used in digital designs, the digital cell library is typically used as is by analog designers, who have no interest in crafting their own flip-flops and NAND gates. However, analog IP, such as bandgap cells or D/A and A/D converters, is seldom used as is by an analog designer. Typically, analog designers will use the IP as a starting point for their own specialized designs, while digital designers can employ the standard IP.

Many power management chips require large MOSFETs with low on-resistance for driving off-chip loads. Optimal layout for such devices is not a simple matter — metal routing, placement of the large device relative to the bond pads and satisfying on-resistance, ESD and latchup conditions simultaneously are common obstacles designers face. By working with a foundry to obtain detailed examples, construction guidelines and specialized consulting, designers can effectively deal with this hurdle.

Most analog chips also require s ome sort of postfabrication trimming to center reference voltages, set oscillator frequency or center some other critical parameter within the chip. There are many approaches for trimming, such as metal fuses, poly fuses, Zener zapping, EPROM and E2PROM, among others. It is possible to implement all of these approaches successfully, but each technique has its own particular advantages that are often learned through hard experience. An experienced foundry will be able to supply complete trimming solutions, from circuit elements in the process development kit through test hardware, test circuitry, component specification and board layouts to help designers over this common barrier.

Specialized and customized training is also a key element of a design-for-success strategy, especially when dealing with a new technology. Such training can cut weeks to months off a designer's learning curve. Design and layout reviews, especially for the first designs submitted in a technology, can also be used to increase an analog designer's success.