VSIA Functional Verification Specification Released to Membership
Document drives reuse in verification environment
Wakefield, MA. – March 22, 2004 – The VSI Alliance (VSIA) today announced that the “Specification for VC/SoC Functional Verification” is now available for VSIA members to download and use. Created by the VSIA Functional Verification Development Working Group (DWG), the document defines a number of common verification approaches, and provides insight into how use by a virtual component (VC) or IP provider could be understood or even reproduced by a VC/IP integrator. In addition to the guidelines normally provided in other VSIA specifications, the functional verification specification includes a list of well-defined rules for good verification practices. The ultimate goal of the specification is to facilitate reuse by the end user of the verification environment delivered by the VC/IP provider for the integration and chip-level verification of an end product. Corporate members involved in the Functional Verification DWG that created this document include: Cadence Design Systems, Elixent, Hewlett-Packard, IBM, Infineon Technologies, Intel, Mentor Graphics, Motorola SPS, Palmchip, Synopsys and Verisity Design.
“While EDA vendors may provide detailed instructions and methodology guides for their specific tools, there has not been much industry activity in establishing more general rules, guidelines and best practices,” said Tom Anderson, Functional Verification DWG Chairperson. “Recognizing this need, a working group with representatives from more than twenty leading semiconductor, system, VC and EDA suppliers has developed a specification for the functional verification of virtual components and the system-on-chip (SoC) designs that use them.”
The functional verification specification includes:
- Best practices for effective functional verification of a VC/IP
- Definitions of the verification-related deliverables that should pass from the VC/IP provider to the VC/IP integrator (SoC team) along with the VC/IP design itself
- A set of detailed rules for these deliverables, including acceptable formats and coding guidelines
- A description of the process for using these deliverables to verify the integrity of the delivered VC/IP
- Description of how certain deliverables can be reused during full-chip SoC verification
- A glossary of terminology related to VC/IP and SoC functional verification methods
Availability
The Specification for VC/SoC Functional Verification Version 1.0 (VER 2 1.0) is currently available for VSIA members to download on the VSIA website at www.vsi.org. Members can download the specification at no cost. This specification may become available to non-members at the end of this year for $750.
About VSIA
The VSI Alliance (VSIA) is an open, international organization that includes representatives from all segments of the SoC industry: System houses, Semiconductor vendors, Electronic Design Automation (EDA) companies, and Intellectual Property (IP) providers. VSIA’s vision is to dramatically improve the productivity of SoC development by specifying open standards and specifications that facilitate the integration of software and hardware Virtual Components from multiple sources. Many companies have adopted the use of VSIA specifications, standards and documents. VSIA has wide industry participation with more than 100 member companies from around the world. Membership is open to any company with an interest in the development and promotion of open standards used in the design of System-on-Chip. For more information, visit the VSIA web site at www.vsi.org.
Adoption of VSIA Specifications and Standards
Adoption and use of VSIA's documents, specifications, and standards is growing at many System-on- Chip companies. Some of the companies that have adopted VSIA specifications and standards include Alcatel; ARM; Cadence Design Systems, Inc.; Fujitsu Limited; Hewlett-Packard Company; Infineon Technologies Corp.; Intel Corp; LogicVision, Inc.; LSI Logic Corp; Mentor Graphics Corp.; Motorola SPS; Nokia Mobile Phones; Oki Electric Industry Co., Ltd.; Philips Semiconductor; sci-worx.; STMicroelectronics Ltd.; Synopsys, Inc.; and Virtual Component Exchange.
The VSI Alliance is a trademark of the Virtual Socket Interface Alliance. All other brands or trademarks are the property of their respective holders and should be treated as such.
Related Semiconductor IP
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
Related News
- elitePLUS semiconductor Technologies released a fully functional 400G PCS VIP.
- NVM Express over Fabrics Specification Released
- Newly Released Versions of DMTF Redfish and SNIA Swordfish Specifications Include NVMe and NVMe-oF Specification Enhancements
- NSITEXE Selects ImperasDV for Automotive Quality RISC-V Processor Functional Design Verification
Latest News
- Axiomise Partners With Bluespec to Verify Its RISC-V Cores
- Rapidus Achieves Significant Milestone at its State-of-the-Art Foundry with Prototyping of Leading-Edge 2nm GAA Transistors
- SEMIFIVE Files for Pre-IPO Review on KRX
- Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the ‘One Stop’ for Memory Interface Solutions
- Synopsys Completes Acquisition of Ansys