Synopsys adds Gain analog USB PHY to core library
 |
Synopsys adds Gain analog USB PHY to core library
By EE Times
November 19, 2001 (10:24 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011119S0021
Synopsys Inc. (Mountain View, Calif.) has added the GT3100 USB 2.0 physical-layer transceiver (PHY) core from Gain Technology Corp. (Tucson, Ariz.) to its DesignWare library.
The Gain GT3100 is USB 2.0-certified by the USB Implementers Forum and, as such, complies with the USB 2.0 specification targeting PCs and peripherals. The offering is also the first analog core included in the DesignWare Star IP program.
The companies believe that the combination of Gain Technology's PHY and Synopsys' device controller core in the DesignWare library will accelerate the development and deployment of USB 2.0 system-on-chip (SoC) solutions.
The companies refer to the combined offering as DesignWare USB 2.0 Macrocell. The device controller half includes the fully synthesizable controller core with a complete verification environment, including bus-functional models, monitors and test suites. The companies claim the device controller core is te chnology-independent and can be targeted to run at all USB 2.0 data rates in FPGAs or ASICs.
The DesignWare USB 2.0 offering will also include views for the Gain GT3100, including the simulation and timing models, with no additional fees or royalties. But users must obtain the implementation views, including GDSII, licensing and support from Gain Technology, for an additional fee.
According to the companies, the GT3100 has a flexible architecture supporting the USB 2.0 480-Mbit/second protocol and data rate, and is backward-compatible with the USB 1.1 protocol at 12 Mbits/s.
According to the companies, at 165-mW absolute maximum power dissipation, the GT3100 provides optimum power dissipation and is suited for low-power, bus-powered functions to operate within the 100-mA limit imposed by the USB 2.0 standard.
A DesignWare one-year technology subscription license is priced at $26,844.
Visit www.synopsys.com/designware/ A> or www.gain.com for more information.
Related Semiconductor IP
- Xtal Oscillator on TSMC CLN7FF
- Wide Range Programmable Integer PLL on UMC L65LL
- Wide Range Programmable Integer PLL on UMC L130EHS
- Wide Range Programmable Integer PLL on TSMC CLN90G-GT-LP
- Wide Range Programmable Integer PLL on TSMC CLN80GC
Related News
- Introducing the Cutting-Edge USB 3.0/ PCIe 3.0 Combo PHY IP Core in 28HPC+ for High-Performance SoC Designs
- Unveiling Silicon-proven USB 3.0 PHY IP Core in 22nm, Elevating High-Speed Data Transmission with Advanced Transceiver Technology, backward compatible with USB 2.0
- USB, MIPI, Ethernet, DisplayPort, PCIe, DDR, HDMI, ONFi Analog Phy IP Cores silicon proven in UMC 28nm & UMC 40nm Process
- GOWIN Semiconductor USB 2.0 PHY Interface and Device Controller IPs Achieve USB-IF Certification
Latest News
- Faraday Reports Full Year 2024 Results
- Cortus MINERVA Out-of-Order 4GHz 64-bit RISC-V Processor Platform targets automotive applications
- Quadric Announces Lee Vick is New VP Worldwide Sales
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google