Synopsys adds Gain analog USB PHY to core library
Synopsys adds Gain analog USB PHY to core library
By EE Times
November 19, 2001 (10:24 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011119S0021
Synopsys Inc. (Mountain View, Calif.) has added the GT3100 USB 2.0 physical-layer transceiver (PHY) core from Gain Technology Corp. (Tucson, Ariz.) to its DesignWare library.
The Gain GT3100 is USB 2.0-certified by the USB Implementers Forum and, as such, complies with the USB 2.0 specification targeting PCs and peripherals. The offering is also the first analog core included in the DesignWare Star IP program.
The companies believe that the combination of Gain Technology's PHY and Synopsys' device controller core in the DesignWare library will accelerate the development and deployment of USB 2.0 system-on-chip (SoC) solutions.
The companies refer to the combined offering as DesignWare USB 2.0 Macrocell. The device controller half includes the fully synthesizable controller core with a complete verification environment, including bus-functional models, monitors and test suites. The companies claim the device controller core is te chnology-independent and can be targeted to run at all USB 2.0 data rates in FPGAs or ASICs.
The DesignWare USB 2.0 offering will also include views for the Gain GT3100, including the simulation and timing models, with no additional fees or royalties. But users must obtain the implementation views, including GDSII, licensing and support from Gain Technology, for an additional fee.
According to the companies, the GT3100 has a flexible architecture supporting the USB 2.0 480-Mbit/second protocol and data rate, and is backward-compatible with the USB 1.1 protocol at 12 Mbits/s.
According to the companies, at 165-mW absolute maximum power dissipation, the GT3100 provides optimum power dissipation and is suited for low-power, bus-powered functions to operate within the 100-mA limit imposed by the USB 2.0 standard.
A DesignWare one-year technology subscription license is priced at $26,844.
Visit www.synopsys.com/designware/ A> or www.gain.com for more information.
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related News
- Unveiling Silicon-proven USB 3.0 PHY IP Core in 22nm, Elevating High-Speed Data Transmission with Advanced Transceiver Technology, backward compatible with USB 2.0
- USB 3.0 PHY IP Cores in 16FFC process technology with High-performance backplane interconnect licensed to a Chinese company for Multimedia SoC application
- Enhance your High-Density data processing capabilities to new heights with the USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP Core interface in 28HPC+/HPC process technology
- Arasan refreshes its Total USB IP Solution with its next generation of USB 2.0 PHY IP
Latest News
- Qualitas Semiconductor Secures Strategic IP Licensing Agreement for MIPI Solutions
- Chinese RISC-V Chipmaker SpacemiT Launches K3 AI CPU, Highlighting the Rise of Open-Source Hardware in Intelligent Computing
- Weebit Nano Q2 FY26 Quarterly Activities Report
- Arasan announces the immediate availability of the industries first xSPI NOR + eMMC NAND Combo PHY IP
- AMIQ EDA Gives AI Agents Access to Essential Design and Verification Data