Philips Business Silicon Hive wins Microprocessor Report Analysts' Choice Awards

- Silicon Hive, a semiconductor IP business in the Philips Technology Incubator, has won the prestigious In-Stat/MDR Microprocessor Report Analysts’ Choice Award for the best Soft-IP Processor Core of 2003. The award, which was presented by analyst Jim Turley last week at a ceremony in San Jose, California (USA), recognized the Avispa+ core as the greatest innovation in embedded core design to have emerged for some time. All the cores nominated for the title of best Soft-IP core came from leading embedded processor companies.

“Silicon Hive’s Avispa+ was by far the most audacious of these CPU and DSP cores” and “incorporates nearly every major processor-design philosophy from the past few decades, from VLIW to RISC and SIMD to CISC” writes Jim Turley in the February 9, 2004 post award ceremony issue of Embedded Processor Watch, adding that the Avispa+ core “should far outrun anything the other vendors have produced.”

“While most of our competitors have been busy adding complex and power-hungry hardware, such as deeper pipelines, larger caches and branch prediction logic to their processors in the hope of increasing performance, we have co-designed the Avispa+ architecture and compiler to achieve higher performance and lower power consumption coupled with a remarkably small silicon footprint,” said Jeroen Leijten, Chief Processor Architect and Co-founder of Silicon Hive. “This award from the world’s leading analyst group in the microprocessor business shows that we have a winning combination of the most parallel embedded VLIW processor and the most aggressive optimizing C-compiler known to date.”

The Avispa+ core embodies all three of Silicon Hive’s key objectives – providing a combination of high performance and low power consumption in highly cost-effective areas of silicon. Even at a power-saving clock frequency of just 150 MHz, Avispa+ gives a peak performance of 9 GOPS (Giga Operations Per Second). Avispa+ can issue 60 new operations every cycle, encoded in a 768-bit ultra-long instruction word (ULIW). Power consumption at this clock frequency is a mere 150 mW and the core only occupies 4 mm2 of silicon when implemented in 0.13-micron CMOS process technology.

The Avispa+ core is principally targeted for orthogonal frequency-division multiplexing (OFDM) based radio applications. In addition to the Avispa family of cores, Silicon Hive is also developing the Moustique and Bresca families of cores. All three families are targeted at software-defined radio and image/video processing applications in mobile communication, consumer and automotive market segments.

The winning of this latest Microprocessor Report Analysts’ Choice award further cements Silicon Hive’s position as a recognized leader in embedded processor technology.

More information on Silicon Hive can be found at http://www.siliconhive.com

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