PCIe 16G May Take Until 2017
Rick Merritt, EETimes
6/23/2015 02:30 PM EDT
SAN JOSE, Calif. — Engineers have 16 GTransfers/second up and running in the lab for PCI Express 4.0, aka Gen 4. The bad news is this is the last turn of the crank for a copper version of the interconnect and, despite progress, a final 1.0 version of the spec may not be ready until early 2017.
Developers in the PCI SIG hope to complete a 0.7 version of the spec by the end of the year, at which stage they expect no major changes to the technology. Getting out ahead of the standard, Cadence and Synopsys will both announce PCI Express 4.0 PHY and controller blocks at the annual PCI SIG conference here June 23.
The big work ahead for the standard is in fine tuning the link and getting engineers to agree on its parameters. The work is significant because the greater speed translates into shorter reach generating some new costs for retimers in some systems such as servers which make heavy use of PCIe.
To read the full article, click here
Related Semiconductor IP
Related News
- Mellanox and Cadence Demonstrate PCI Express 4.0 Multi-Lane PHY IP Interoperability
- Synopsys Optimizes DesignWare IP for PCI Express 4.0 Architecture to Reduce Latency by up to 20 Percent
- PLDA Announces Gen4SWITCH - The Industry's First PCI Express 4.0 Platform Development Kit (PDK)
- Synopsys and Mellanox Demonstrate Complete PCI Express 4.0 Host and Device System Interoperability
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack