MorethanIP releases the industry's first Ethernet L2 Switch Engine for Programmable Logic Devices and structured ASIC
Karlsfeld September 21, 2004
-- MorethanIP releases the industry's first Ethernet L2 Switch Engine for Programmable Logic Devices and structured ASIC. Following the introduction of the TCP/IP Acceleration Solution, MorethanIP introduces a new System Level IP Core which is designed to achieve an even higher level of integration by implementing Ethernet switching capabilites into FPGA and ASIC.
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
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Related News
- MorethanIP, announces several new cores for the Ethernet application space for proprietary 2.5 Gbps Ethernet and an improved Ethernet Switch Core with quality of service support
- Faraday and MorethanIP Enter Partnership for 10GbE/XAUI & IEEE 1588 Ethernet IP Cores for ASICs and Structured ASIC Engagements
- eASIC and MoreThanIP Partner to Deliver Tri-Mode (10/100/1000) Ethernet MAC Solutions for Nextreme Structured ASICs
- Altera, National Semiconductor and MorethanIP Announce First 8-Port Switch Development Board With IEEE 1588 Timing Control
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