Evatronix Releases JPEG 2000 Image Compression Encoder Optimized for FPGA Designs

The silicon Intellectual Property (IP) provider, Evatronix SA, announced today the availability of the JPEG 2000 Encoder IP core. The encoder has been optimized for FPGA designs and takes a minimum number of slices while providing full compatibility with ISO/IEC 15444-1 standard that defines the JPEG 2000 format.

The Evatronix JPEG 2000 Encoder IP core goes beyond the resolution limit for processed images (usually 4096 x 4096 pixels) and allows pictures of virtually any resolution to be compressed. It is one of the very first JPEG 2000 encoders to allow processing of Ultra HD images (7680 x 4320 pixels).

Other benefits include configurability of image’s tile size, which can be adjusted to user’s needs and thus significantly increase compression efficiency. As the tile parts are interlaced in the codestream, the available progression applies to the whole image. Also, for even more control over the quality of a final result, compression level can be set through configuration of a bunch of parameters.

Full hardware implementation of TIER-1 and TIER-2 EBCOT encoder allows setting up to 32 different arithmetic entropy coding styles, which give user the ability to precisely set size and quality of output bitstream while eliminating the need to employ any external CPU.

Implementation of optimal estimation for transaction rates and up to 7 DWT decomposition levels further increase the core’s ability for customization towards a specific application.

The Evatronix JPEG 2000 Encoder implements three clock cycles per sample and is guaranteed to achieve a minimum of 35 megasamples per second in vast majority of Xilinx Virtex 5 FPGAs when running at a standard rate of 100 MHz. This result, however, applies to slower lossless compression process.  

“With such a rapid evolution of available image resolution, the need for highly efficient image compression is bigger than ever before”, said Adam Bitniok, the JPEG 2000 Encoder developer at Evatronix. “With Evatronix solution eliminating so many constraints for the JPEG 2000 encoders, we are broadening the scope of applications our customers might use this IP in.”

Availability and optimization options

The JPEG 2000 Encoder IP core is available now for implementation in any FPGA technology, however, RTL source code for ASIC implementations can also be licensed. The core offers a variety of configurable options, and the basic version is priced at $47.000 for a single use FPGA license.

About JPEG 2000

JPEG 2000, introduced as a successor of a very popular JPEG format, is superior to his predecessor in a number of features. The flexibility and scalability of codestream, which allows its ordering in variety of ways, significantly increases application performance. The format is exceptionally efficient in lossy compression of images. Ability to produce progressive bitstreams and random access to the block level make JPEG 2000 a perfect solution for such applications as digital libraries or prepress tools.

About Evatronix

Evatronix SA, founded in 1991 in Poland, develops electronic virtual components (IP cores) along with complementary software and supporting development environments. The company also provides electronic design services. Product lines cover a multitude of solutions from interface controllers and microprocessors to integrated System-on-Chip development platforms.
Evatronix IP cores are available directly or through the sales network of its strategic distribution partner, CAST, Inc.
Evatronix is headquartered in Bielsko-Biala, Poland, and employs over 75 engineers.
For more information about the company please visit the company’s web site at www.evatronix.pl or contact Jacek Duda at +48322311171 ext. 22 or jacek.duda(at)evatronix.pl.