Intel processor integrates North Bridge components

Intel processor integrates North Bridge components
By Will Wade, EE Times
August 31, 2000 (5:44 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000830S0012

SAN JOSE, Calif. — Intel Corp. is focusing its engineering skills on a highly integrated device that incorporates both a graphics engine and a Rambus memory controller into a single processor chip aimed at the low-cost PC segment. Known as the Timna, the device is expected to launch early next year. The Santa Clara, Calif., company gave a sneak peek at the design at the recent Intel Developer Forum trade show.

"We are designing the Timna for the low-cost, value PC market," said Ilan Spillinger, a principal engineer at Intel and head of the Israel-based design team working on the chip. Implemented at the 0.18-micron production level, the design is essentially recycling many of the elements already in use today. It is based on the same processor core as the Katmai-class MPUs that began shipping in 1999 as the first generation of the Pentium III. It also features the same graphics engine currently used in Intel's integrated 810 chip set, and the s ame 128-kbyte Level 2 cache used in the current generation of Celeron chips, Intel's primary entry in the low-cost PC segment today.

Although the Timna will feature a memory controller to use Rambus DRAM technology, the company also plans to ship an external device alongside the Timna that translates RDRAM signals into a format that will allow the processor to be used in systems with standard SDRAM. At first blush, this strategy might seem like another sign that Intel is backing away from steadfast support of RDRAM. But Dean McCarron, principal analyst for Mercury Research (Scottsdale, Ariz.), said that "incredible as it may seem," this has always been the plan.

"I first saw the specs for this part three years ago, and even then it had the RDRAM controller and an external SDRAM translator," McCarron said.

The keys to this contradiction are cost and bandwidth. Spillinger said the main reason for the integrated RDRAM controller is not to use Rambus chips, but to allow the most data to get shuttled on and off the processor with the fewest pins. Timna is all about cost. Using fewer pins allows for less expensive packaging, which in turn cuts production costs and delivers lower prices to the end user.

As McCarron explained, an RDRAM controller uses 16 pins running at 800 MHz, allowing a maximum bandwidth of 1.28 Gbytes/second. Using an SDRAM controller would have required four times as many pins and yielded only half the bandwidth. "Using more pins has a direct correlation to increased packaging costs," McCarron said. "You just get a lot more bang for your pin with Rambus."

At this point, nobody is under any illusion that the Timna will end up in systems using Rambus memory chips. "The market can't currently support that because of the [RDRAM's] price premium," said Spillinger.

< ahref="http://www.intel.com/">Intel already has one component available to translate data from an RDRAM controller into SDRAM signals, but that part was recently found to have some design glitches and is being revamped. The newer version is likely to be the one that is eventually used with the Timna.

One point that McCarron questioned was the timing of the launch. Intel expects Timna to debut in the first quarter of next year at speeds north of 600 MHz. Putting all the processor's component parts on a single die would seem to make for a large die size, a fact almost certain to lead to lower yields. And the value market Intel is aiming it at means low prices and low margins.

Given these facts, McCarron wondered why Intel would allocate wafers to the Timna when the same wafer could generate much more revenue, and profit, with Pentium III or Pentium 4 chips? He pointed out that in today's market, customers are snapping up processors about as fast as Intel and its competitors can turn them out.

Also, McCarron questioned how the Timna will compare on the performance front. The Katmai core has proven itself, but the graphics engine used in the 810 chip set was considered second-rate when it launched 18 mon ths ago, and now will be even more lackluster compared with some of the whizzy graphics cores that have since appeared. And the effort to translate every memory signal moving from the processor to the main system memory — the controller's job — will certainly lead to a performance hit, he said.

But luckily for Intel, nobody is likely to care. "The Timna is all about cost," said McCarron. "Since when has anybody cared about performance at this end of the market? And if Timna is successful, I have no doubt that it will be upgraded quickly."