Genesys Testware introduces built-in diagnosis and repair solution for embedded memories with repair circuitry

Atlantic City, NJ, (October 3, 2000) - Genesys Testware, Inc. today introduced the first commercial Built-In Self-Test, Diagnosis and Repair (BISTDR) for embedded memories with spare cells and repair circuitry. "The leading edge ICs that power the communications systems for the new internet infrastructure contain several megabits of embedded SRAMs and DRAMs. Our unique BISTDR solutions can be used to reduce the unit cost of ICs with large embedded memories by improving their yield without expensive investments in laser fuse blowing equipment. We are pleased to announce Memory BistCore Ultra TM which can be used to implement BISTDR without any performance penalty by exploiting the capabilities of embedded memories with spare cells and repair circuitry", said Bejoy G. Oomman, President of Genesys Testware.

Memory BistCore Ultra is a library of parameterized, synthesizable, register transfer level (RTL) BISTDR components. The user interacts with Memory BistCore Ultra TM using Gtshell TM BIST IP integration tool. The user writes short Tool Command Language (Tcl) scripts to describe the memories in the IC and repair resources contained in each such memory. Gtshell has built-in Tcl functions that automate the integration of Memory BistCore Ultra with popular memory compilers, synthesis tools, and simulators.

"We are pleased to hear that Genesys Testware has added support for Virages Custom-Touch STAR (Self-Test and Repair) family of SRAM compilers to their Memory BistCore Ultra product", said Vin Ratford, Vice President of Marketing at Virage Logic the leading embedded memory IP company. "We are developing SRAM compilers with embedded repair circuitry that seamlessly interface with BISTDR circuitry in Memory BistCore Ultra", said Mo Tamjidi, President of Dolphin Technologies, a leading memory compiler vendor. "We are excited to learn that Genesys Testware has added support for the fuse box architecture in Silicon Magic embedded DRAMs to their Memory BistCore Ultra product ", said Rajeev Jain, Test and Product Engineering manager at Silicon Magic, a leading embedded DRAM company. Existing users of Memory BistCore Professional product can take advantage of these new capabilities by changing a few lines in their existing Gtshell Tcl scripts. Memory BistCore Ultra also supports Built-In Self-Test (BIST) of SRAMs, register files, and ROMs. IC Designers can easily integrate Memory BistCore into their design flow since it is a complete embedded memory test solution that is process, foundry, tester and platform independant.

The BISTDR circuit identifies faulty address and data locations and remaps them to spare rows and columns in the memory array using the repair circuitry inside the memory array. BISTDR circuits have to be activated every time the IC is powered up to recalculate faulty memory cells and reconfigure the embedded memory. Memory BistCore Ultra contains power on sequencing circuitry to  co-ordinate these operations. This further simplifies the job of integrating Memory BistCore Ultra with embedded memories with repair circuitry. The results of the BISTDR operation can also be shifted out during the manufacturing test to simplify failure analysis and yield enhancement acitivities. Memory BistCore Ultra can be easily interfaced to IEEE 1149.1 compliant test controllers which support BIST instructions like Boundary ScanCoreTM.
Genesys Testware currently provides the TestCoreTM family of products including Memory BistCore for Built-In Self-Test, Diagnosis and Repair (BISTDR) of embedded memories, Boundary ScanCore for board test, core test integration and test pattern reuse and Logic BistCore for BIST of hard cores and on-chip logic to System on Chip (SOC) designers. Each component in TestCore is a library of parameterized, synthesizable, RTL designs. Gtshell is a Tcl based behavioral test synthesis tool that automates the insertion of TestCore into a design. TestCore and Gtshell are licensed as an IC Component Design and as a behavioral test synthesis tool respectively on a site-wide basis to IC design groups using an EDA tool business model. Memory BistCore Ultra is priced starting from $120,000 for a typical design site.

Genesys Testware, Inc. was founded in October 1995 to improve the productivity of designers of large ICs, by providing comprehensive embedded manufacturing test and debug solutions. Its unique TestCore family of products has been successfully used in many customer designs.

For more information on Genesys Testware or its products, please contact Bejoy G. Oomman, Genesys Testware, 76 Whitney Place, Fremont, CA 94539. Telephone : 510-661-0791, Fax: 510-498- 8734, e-mail: bejoygo@genesystest.com, URL: http://www.genesystest.com.