Dolphin, Raisonance team to support 8051 controller core
![]() |
Dolphin, Raisonance team to support 8051 controller core
By Peter Clarke, EE Times
April 9, 2001 (1:41 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010409S0041
LONDON Dolphin Integration SA and Raisonance SA have teamed up to create a so-called "hierarchical" development system for the 8051 8-bit microcontroller core, which is available for license from Dolphin. In support of the Flip8051 core, the two companies have linked their proprietary simulators Dolphin's Smash HDL and mixed-signal simulator, and Raisonance's Sim-Ice instruction-set simulator. The hierarchical system provides tools for HDL simulation, for instruction-set simulation and for breadboard support that are designed to work with an emulator based on an FPGA implementation of the core, rather than the usual bonded-out chip. "The move to system-on-chip [SoC] has a consequence for emulators. If you have to introduce a new emulator every time there is a little change in the core, you are doomed," said Michel Depeyrot, chief executive officer of Dolphin Integration (Meylan, France)< /A>. "We treat the target as an SoC, not as a microcontroller, so now it is hierarchical, with one FPGA emulating the core, one providing the tracing function and the peripherals emulated on a breadboard." The Flip8051 was developed by Richard Watts Associates Ltd. (Leighton Buzzard, England) and was acquired by Dolphin in August 1999. Using FPGAs and FPGA arrays in emulators is not uncommon, though it usually involves a reduction in emulation speed. "We believe we can get to the largest part of the market with this. The interaction between CPU and peripherals is not that high," said Depeyrot. Lockable interface Dolphin and Raisonance (Grenoble, France) have also patented a form of lockable debug interface intended to prevent piracy of ROM code or design data through the emulation port that is usually present even in packaged systems. The patented system lets the program developer authoriz e memory read or write operations on either data memory or program memory embedded with any microprocessor in a system-level chip, Dolphin claims. The protection mechanism is generally applicable to any processor core and to any serial or parallel debug interface, whether wired or wireless. "The threat comes from the capability to link an emulator by RF; to perform downloading and uploading from and to information appliances. The patent works by having an access code. It's a software-controlled hardware for locking the system, so you control who uses the interface," said Depeyrot. "It's a general-purpose interface, but we are applying it to the JTAG debugging interface. Other people can use it, but they will have to license it from us."
Related Semiconductor IP
- Xtal Oscillator on TSMC CLN7FF
- Wide Range Programmable Integer PLL on UMC L65LL
- Wide Range Programmable Integer PLL on UMC L130EHS
- Wide Range Programmable Integer PLL on TSMC CLN90G-GT-LP
- Wide Range Programmable Integer PLL on TSMC CLN80GC
Related News
- Digital Blocks AMBA Peripherals I3C, I2C, eSPI, xSPI Controller IP Core Families Extend Leadership with enhancements containing feature-rich, system-level integration features.
- MIPI M-PHY 4.1 IP, UFS 3.1 Controller IP & Unipro 1.8 Controller IP Cores are available for instant licensing to support your total UFS applications
- New controller IP core for secure data
- Production-proven CAN Controller IP Core, equipped with a Safety package (Safe DCAN-FD, ISO 26262: Safety manual, FMEDA), tailored specifically for High-End Automotive and Consumer Applications is available for immediate licensing
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing