Is design and reuse an impossible dream, ask panelists
Anne-Francoise Pele, EE Times
(12/03/2009 4:03 PM EST)
GRENOBLE — A panel session at the IP-ESC 2009 Conference this week in Grenoble, France, examined IP design and reuse from a business and technology perspective and urged IP and SoC providers to reach compromises.
With the global economic downturn, SoC designers became aware that by outsourcing critical IP they could decrease design time and improve time-to-market. However, collaboration between the IP vendor and the customer must be established, especially if IP reuse is to be achieved. In his introductory talk at the panel session, Jack Browne, senior vice president of sales and marketing at Sonics, said he sees a clear disconnection between the IP and SoC providers and called for a change to manage expectations on both sides.
To read the full article, click here
Related Semiconductor IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
Related News
- Arteris Addresses Silicon Design Reuse Challenge with New Magillem Packaging Product for IP Blocks and Chiplets
- AMIQ EDA Gives AI Agents Access to Essential Design and Verification Data
- SmartDV and Mirabilis Design Announce Strategic Collaboration for System-Level Modeling of SmartDV IP
- Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification
Latest News
- Seligman Ventures Leads Cognichip’s $60M Series A to Back Physics-Informed AI for Chip Design, Intel CEO Lip-Bu Tan and Seligman Ventures’ Umesh Padval Join the Board
- SEMI Projects Double-Digit Growth in Global 300mm Fab Equipment Spending for 2026 and 2027
- Intel to Repurchase 49% Equity Interest in Ireland Fab Joint Venture
- AGI CPU: Arm’s $100B AI Silicon Tightrope Walk Without Undermining Its Licensees
- EnSilica selected for UK CHERI Adoption Collective