Is design and reuse an impossible dream, ask panelists
Anne-Francoise Pele, EE Times
(12/03/2009 4:03 PM EST)
GRENOBLE — A panel session at the IP-ESC 2009 Conference this week in Grenoble, France, examined IP design and reuse from a business and technology perspective and urged IP and SoC providers to reach compromises.
With the global economic downturn, SoC designers became aware that by outsourcing critical IP they could decrease design time and improve time-to-market. However, collaboration between the IP vendor and the customer must be established, especially if IP reuse is to be achieved. In his introductory talk at the panel session, Jack Browne, senior vice president of sales and marketing at Sonics, said he sees a clear disconnection between the IP and SoC providers and called for a change to manage expectations on both sides.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related News
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
- Agnisys Joins Arm Partner Program and Releases Solution Brief for Functionally Safe Arm-Based SoC Design
- Enosemi and GlobalFoundries announce the availability of silicon-validated electronic-photonic design IP available in the GF Fotonix platform
- Omni Design Technologies extends partnership with EnSilica and expands Swift™ Data Converter IP portfolio
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers