Augusta Technology Selects Denali Databahn IP for its Mobile Multimedia Processor

LPDDR1-SDRAM Controller and PHY Solution Enables 30 Percent Power Savings For Pocket TVs and Portable Media Players

SUNNYVALE, Calif., April 14, 2010 — Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that Augusta Technology USA, a mobile digital solutions company, has selected Denali’s Databahn™ LPDDR1-SDRAM controller and PHY intellectual property (IP) products for incorporation into its latest processor, designed using TSMC’s Low Power (LP) process technology. The low-power processor solution enables mobile manufacturers to cost-effectively incorporate digital broadcast TV reception and other popular multimedia features into various portable devices such as cellular phones, portable media players, pocket TVs, smartphone PDAs, and vehicle media centers. Augusta’s engineers are using the unique power-saving features available in Denali’s LPDDR controller and PHY to achieve optimal system-level performance for the DRAM subsystem in Augusta’s processor design.

“As a provider of leading-edge mobile digital solutions, we are always looking to take advantage of the latest advances in low-power technologies,” said Aki Shohara, CTO at Augusta Technology USA. “Our engineers who have extensive and successful silicon design experience for mobile solutions, particularly with respect to power-saving optimization, selected Denali’s Databahn controller and PHY for our next mobile chip after careful evaluation. Denali’s high-quality LPDDR controller, PHY solutions and domain expertise were key factors in the selection to achieve our design requirements and to meet our time to market goals.”

The low-power features of Denali’s Databahn DRAM controller and memory PHY allow mobile systems to manage memory power usage either automatically or manually, whichever best suits the overall system design and power/performance goals. Databahn’s high-performance algorithms improve memory utilization. When combined with low-power IC process technology, systems can extract high-bandwidth performance from DRAM subsystems while operating them at low power. The PHY incorporates a digital delay locked loop (DLL) that reduces power consumption while still achieving high-performance design goals. In addition, IC designers find the PHY’s DLL easy to implement in silicon. The PHY’s low-power architecture combined with the memory controller’s intelligent management of the low-power modes built into commercial DDR memory cuts memory-subsystem power consumption by 30%. These advanced DRAM-management technologies and more will be highlighted at the upcoming MemCon event, “Roadmap: GHZ DDR3 and Beyond,” on July 28th, in Santa Clara, CA.

“Next-generation mobile SoCs that incorporate specialized DDR memory systems must deliver low-power features with very high-quality and within tight market windows,” states Marc Greenberg, director, technical marketing of IP products for Denali Software. “Our Databahn controller and PHY IP products not only provide optimal configurability and quality, but also incorporate flexible power-management options for a variety of next-generation portable digital television applications. We are pleased to have been able to work with Augusta Technology and help them meet their aggressive time-to-market schedules.”

About Databahn DDR Memory Solutions

Together, Denali's Databahn DDR controller and PHY constitute a complete solution that’s ready to be integrated into SoCs and ASICs. They ensure compatibility with all the latest high-speed, low-power memory technologies. This combination supports all memory component specifications, including all the latest DDR3/2/1 and LPDDR2/1 devices from all major memory vendors and support for all vendor process nodes. The PHY is configurable for data width, ECC, low power, and other options, and is delivered to match the unique requirements of a specific DDR application. For more info, visit: www.denali.com/databahn.