ISSCC panel sees challenges at 20-nm
Mark LaPedus, EETimes
2/23/2011 9:02 PM EST
SAN FRANCISCO – After some debate, there is finally some consensus at the 22-/20-nm logic node-at least among leading-edge foundries.
During a panel session at the 2011 International Solid-State Circuits Conference (ISSCC) here, IBM, Globalfoundries and TSMC all agreed that they would extend planar bulk CMOS to the 22-/20-nm node. In other words, don’t expect foundries to embrace FinFETs, fully depleted SOI, multi-gate transistors or other newfangled structures at 22-/20-nm.
To read the full article, click here
Related Semiconductor IP
- Simulation VIP for Ethernet UEC
- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
- Simulation VIP for UALink
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- JPEG XL Encoder
Related News
- intoPIX Solutions Tackle the Biggest Challenges in Automotive Imaging at ADAS & Autonomous Vehicle Expo 2024
- Standards group VSIA focuses on adoption challenges
- SIA road map defines performance-SoC challenges
- Object-based video coding challenges MPEG
Latest News
- Spectral Design and Test Inc. and BAE Systems Announce Collaboration in RHBD Memory IP Development
- VSORA and GUC Partner on Jotunn8 Datacenter AI Inference Processor
- Mixel MIPI IP Integrated into Automotive Radar Processors Supporting Safety-critical Applications
- GlobalFoundries and Navitas Semiconductor Partner to Accelerate U.S. GaN Technology and Manufacturing for AI Datacenters and Critical Power Applications
- VLSI EXPERT selects Innatera Spiking Neural Processors to build industry-led neuromorphic talent pool