ISSCC panel sees challenges at 20-nm
Mark LaPedus, EETimes
2/23/2011 9:02 PM EST
SAN FRANCISCO – After some debate, there is finally some consensus at the 22-/20-nm logic node-at least among leading-edge foundries.
During a panel session at the 2011 International Solid-State Circuits Conference (ISSCC) here, IBM, Globalfoundries and TSMC all agreed that they would extend planar bulk CMOS to the 22-/20-nm node. In other words, don’t expect foundries to embrace FinFETs, fully depleted SOI, multi-gate transistors or other newfangled structures at 22-/20-nm.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- MIPI SoundWire I3S Peripheral IP
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
- LPDDR6/5X/5 Controller IP
- Post-Quantum ML-KEM IP Core
Related News
- intoPIX Solutions Tackle the Biggest Challenges in Automotive Imaging at ADAS & Autonomous Vehicle Expo 2024
- Standards group VSIA focuses on adoption challenges
- SIA road map defines performance-SoC challenges
- Object-based video coding challenges MPEG
Latest News
- ANAFLASH Advances Embedded FLASH Memory for Next-Generation Smart Edge Devices with Samsung Foundry
- SEMI Reports Global Silicon Wafer Shipments to Rebound 5.4% in 2025, with New Record Expected by 2028
- Intel Eyeing AI Catchup in Inference with SambaNova Acquisition
- ADTechnology Collaborates with Euclyd to Develop Ultra-Efficient AI Chip for Datacenters
- SEALSQ and IC’Alps Unify Expertise to Deliver Integrated Post-Quantum Cybersecurity and Functional Safety for Autonomous Vehicles