ISSCC panel sees challenges at 20-nm
Mark LaPedus, EETimes
2/23/2011 9:02 PM EST
During a panel session at the 2011 International Solid-State Circuits Conference (ISSCC) here, IBM, Globalfoundries and TSMC all agreed that they would extend planar bulk CMOS to the 22-/20-nm node. In other words, don’t expect foundries to embrace FinFETs, fully depleted SOI, multi-gate transistors or other newfangled structures at 22-/20-nm.
To read the full article, click here
Related Semiconductor IP
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
- JESD204E Controller IP
Related News
- Standards group VSIA focuses on adoption challenges
- SIA road map defines performance-SoC challenges
- Object-based video coding challenges MPEG
- Verisity, 0-In and Novas Announce Strategic 'VPA' Collaboration to Address Nanometer SoC Verification Challenges
Latest News
- RaiderChip showcases the evolution of its local Generative AI processor at ISE 2026
- ChipAgents Raises $74M to Scale an Agentic AI Platform to Accelerate Chip Design
- Avery Dennison announces first-to-market integration of Pragmatic Semiconductor’s chip on a mass scale
- Ceva, Inc. Announces Fourth Quarter and Full Year 2025 Financial Results
- Ceva Highlights Breakthrough Year for AI Licensing and Physical AI Adoption in 2025