Altera POS-PHY cores suit PMC-Sierra products
Altera POS-PHY cores suit PMC-Sierra products
By Michael Santarini, EE Times
August 14, 2000 (11:01 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000814S0008
Altera Corp. (San Jose, Calif.) has announced a family of cores that are compatible with PMC-Sierra's line of POS-PHY Level 3 products.
According to the company, the first core in the family is currently shipping to selected top-tier network infrastructure customers using PMC-Sierra products for the new generation of super routers and Layer 3 switches that are required for next-generation, multiservice voice and data networks.
Altera also announced that it will continue to work closely with PMC-Sierra to ensure that future core offerings have device compatibility with POS-PHY Level 3 and beyond. The company said it is currently participating in the definition of the POS-PHY Level 4 standard.
Altera's POS-PHY Level 3 cores are designed for use in link-layer or physical-layer devices that transfer data to and from POS devices using the standard POS-PHY interface.
The MegaCore functions comprise separately configurable mo dules that may be combined via Altera's MegaWizard Plug-In tool to generate a parameterized module that allows POS-PHY-compliant interfaces to be included in custom designs, said Altera.
The MegaCore function supports POS-PHY Level 3 operating at greater than OC-48 line speeds (2.5 Gbits/second), enabling efficient translation between the different formats, including mapping between different bus speeds and bus widths, as well as customizable FIFO parameters.
The POS-PHY Level 3 function consists of two separate MegaCore products-the PHY layer (ordering code: PLSM-POSPHY/P3) and the Link layer (PLSM-POSPHY/L3). The Link layer core and the PHY layer core will be fully released by the fourth quarter, and both are priced at $12,995 each. For further information visit www.Altera.com.
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related News
- Unleashing the Full Potential of Your Display: eDisplayPort v1.4 PHY and Controller IP Cores are available for licensing for your Robust products
- Unlock the Power of DisplayPort v1.4 Tx/Rx PHY and Controller IP Cores: Maximize the Potential of Your Next-Generation Products
- Augment your Peripheral slot's performance with the Low Power and High Throughput PCIe 4.0 PHY IP Cores in 12FFC with matching PCIe 4.0 Controller IP Cores
- Elevate your High-speed data transmissions to the next level for all Display interfaces with the MIPI D-PHY/ LVDS Combo PHY IP Cores in 40nm
Latest News
- Jim Keller: ‘Whatever Nvidia Does, We’ll Do The Opposite’
- FlexGen Streamlines NoC Design as AI Demands Grow
- IntoPIX Presents Its New Titanium Software Suite: Empowering AV-Over-IP Workflows With Speed, Quality & Interoperability
- Global Semiconductor Sales Increase 2.5% Month-to-Month in April
- Speedata Raises $44M to Launch First-Ever Chip Designed Specifically for Accelerating Big Data Analytics - Compute's Second Largest Workload