Altera IP supports AES

To ensure the secure transmission of information and to defeat hackers, the Rijndael intellectual-property cores use a higher number of bits for encrypting each key than the Data Encryption Standard, Altera said. Earlier this year, the National Institute of Standards and Technology chose the Rijndael algorithm to replace DES as the new AES standard.

Altera's high-speed Rijndael encryption/decryption core supports block and key lengths of 128 bits. Two versions are available: one with 128-bit parallel inputs a nd outputs, and the other with a 16-bit-wide multicycle access bus for all I/O.

The high-speed Rijndael decryptor core runs at over 1.1 Gbits/second and can be implemented in Altera's Apex 20K100E device.The low-speed core supports key lengths of 128, 192 and 256 bits and block lengths of 128, 192 and 256 bits. Altera said that the low-speed Rijndael decryptor core runs at over 40 Mbits/s and can be implemented in the Apex 20K30E devices. The cores are priced at $9,995.

Altera's IPsec solution comes in the form of two cores in its IP Megastore: The Secure Hash Algorithm (SHA-1) and Message Digest Algorithm (MD5) have been added to Altera's existing certified DES and Triple-DES cores to provide a "complete system-on-a-programmable-chip solution for IPsec applications," the company said.

The MD5 algorithm conforms to RSA MD5 message digest algorithm, which generates a 128-bit message digest or hash function of an arbitrary-length input and is used for digital signature applications. Th e price is $5,995. The SHA-1 function implements the secure hash algorithm as described in FIPS PUB 180-1 and generates a 160-bit message digest or hash function of an arbitrary-length input. The core is priced at $5,995.

All these cores can be downloaded from (www.altera.com/ipmegastore.)

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Eureka Technology has released a suite of PowerPC cores for the Cypress Delta39K family of complex programmable-logic devices. The three cores-a bus master, bus slave and arbiter-target high-end communications systems, including routers, switches, control plane processors, servers and terminals.

The PowerPC Bus Master, called the EP201, is designed to initiate read/write data transfers on the PowerPC CPU host bus. It is typically connected to a DMA controller, bus-snooping or peripheral-bus device such as PCI. The PowerPC Bus Slave, EP100, is designed as a target for CPU or other bus master access. It can be used as an interface b etween the CPU and the system's core logic, memory subsystem or peripheral device such as a PCI host bridge.

See (www.eurekatech.com/partners/cypress.htm.)