Alatek Boosts Performance of Mentor Graphics® HDL Simulators By 100x

Seamless Integration

The DVM software automatically recreates design hierarchy, allowing the user to select any hierarchical RTL block to be accelerated in hardware. The RTL blocks in hardware and software communicate with one another on an event-by-event basis using PLI and FLI communications protocols and providing huge speed improvement without any manual operations.

"One of the nicest features of HES is its tight integration with the ModelSim design manager. Appearing as an icon within ModelSim, it allows launching of design acceleration without any additional manual operations or compilations by ModelSim," stated Bob Fess, Alatek General Manager.

Superior Performance

The acceleration of RTL designs by the HES product depends upon the design's architecture. Laboratory tests have shown acceleration of processor IP cores in excess of 100x and some communications IP cores, such as filters, were simulated over 500x faster than by the ModelSim RTL simulators operating without the HES accelerators.
 

Multi-Million Gate Support

Since the majority of the HES technology resides in software, HES boards are extremely small. Unlike other hardware accelerators, HES accommodates 2 million gates into a 4"x6" area and 8 million gates into a 4"x10" area. The boards can be interconnected with a flex cable, forming larger design acceleration units, up to 32 million gates.

The HES boards come with optional daughter boards that can accommodate additional memories, processors, DSPs and ASICs. These devices can be simulated together with any HDL design blocks residing within the ModelSim environment.

The HES hardware verification accelerator is targeted toward designers of ASICs, SoCs, and large FPGAs who wish to speed their products to the market. Alatek selected ModelSim because of its wide acceptance by designers of advanced and performance-critical products. All ModelSim users can benefit from the HES technology, particularly those who work on high quality and time-to-market sensitive products.
 

Pricing and Availability

Hardware Embedded Simulation (HES) includes the first year of software maintenance in the purchase price. HES products supporting 2 million FPGA gates start at $125,000. Various hardware configurations are available, and boards that support up to 6 million FPGA gates will be available in 4thQTR of 2001. To obtain additional information on both HES and Incremental Prototyping, please contact Alatek at info@alatek.com.
 

About Alatek

Since its inception in January 1997, Alatek has specialized in the development of hardware accelerators and intellectual property (IP) cores. Alatek has an OEM business model for hardware accelerators and direct sales model for the IP cores and design services. It is currently supplying Alatek with HES hardware accelerators and pursuing similar OEM opportunities with other simulator vendors. Alatek offers high quality, low cost synthesizable cores for devices such as micro-controllers, PC peripherals, bus interfaces, and free simulation models. Having broad expertise in design simulation and verification, particularly for Altera and Xilinx FPGA structures, Alatek operates as a full-service design house. Alatek is a privately held company with offices in Nevada serving the U.S. and Asia and offices in Poland serving the European market. For additional information, visit Alatek's website at www.alatek.com.

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