HBM IP Listing

HBM Memory Model provides an smart way to verify the HBM component of a SOC or a ASIC.

• Controller

HBM DFI Verification IP provides an smart way to verify the HBM DFI component of a SOC or a ASIC.

• Verification IP
• Controller

The HBM4 Verification IP provides an effective & efficient way to verify the components interfacing with HBM interface of an ASIC…

• Verification IP
• Controller

HBM Synthesizable Transactor provides a smart way to verify the HBM component of a SOC or a ASIC in Emulator or FPGA platform.

• Controller

HBM DFI Synthesizable Transactor provides a smart way to verify the HBM DFI component of a SOC or a ASIC in Emulator or FPGA plat…

• Controller

The HBM 3 Verification IP provides an effective & efficient way to verify the components interfacing with HBM interface of an ASI…

• Verification IP
• Controller

Produced by DRAM manufacturers such as Samsung and Micron, High Bandwidth Memory or HBM, provides users with high bandwidth, low …

• Controller

Comprehensive memory model and PHY verification HBM VIP is a comprehensive memory VIP solution portfolio for high bandwidth memor…

• Verification IP
• Controller

In production since 2015 on dozens of production designs.This Cadence® Verification IP (VIP) provides support for the JEDEC® High…

• Verification IP
• Controller

DFI HBM Assertion IP provides an efficient and smart way to verify the DFI HBM designs quickly without a testbench.

• Controller

HBM Assertion IP provides an efficient and smart way to verify the HBM designs quickly without a testbench.

• Controller

Massive memory bandwidth, the simplicity of an AXI Interface, no need for external pins HBM IP, made available for Virtex UltraSc…

• Controller

This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide …

• Controller + PHY + 1
• TSMC
• 5nm
• N5FF
• Silicon Proven

This datasheet describes GUC’s HBM (High Bandwidth Memory) PHY IP, which can be integrated with HBM memory controller to provide …

• Controller + PHY + 1
• TSMC
• 16nm
• Silicon Proven

This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow.

• TSMC
• 7nm
• N7+
• Available on request

This specific IP macro is designed in TSMC 65nm and can be ported to other technologies upon request using Sofics in-house design tool flow.

• TSMC
• 65nm
• LP
• Available on request

This TSMC 3nm 1.8V, 1.2V and 0.9V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins.

• TSMC
• 5nm
• N5
• Available on request

This TSMC 3nm 3.3V ESD Local Clamp provides compact, low-capacitance on-chip ESD protection for sensitive I/O and interface pins.

• TSMC
• 3nm
• N3A
• Available on request

This TSMC 3nm 1.2V ESD Local Clamp provides low-capacitance, low-leakage on-chip ESD protection for sensitive I/O and high-speed interface pins.

• TSMC
• 3nm
• N3A
• Available on request

This TSMC 22nm 5.5V ESD Power Clamp provides low-leakage protection for sensitive supply and interface pins.

• TSMC
• 22nm
• ULL
• Available on request