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HBM Memory Model

Overview

HBM Memory Model provides an smart way to verify the HBM component of a SOC or a ASIC. The SmartDV's HBM memory model is fully compliant with standard HBM Specification and provides the following features. Better than Denali Memory Models.

HBM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

HBM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports HBM memory devices from all leading vendors.
  • Supports 100% of HBM protocol standard JESD235, JESD235A, JESD235B, JESD235C and JESD235D.
  • Supports all the HBM commands as per the specs.
  • Supports programmable clock frequency of operation.
  • Supports all types of timing and protocol violation detection.
  • Supports burst length of 2 and 4.
  • Supports Programmable READ/WRITE Latency timings.
  • Supports Bank grouping.
  • Supports 8, 16, 32, 48 and 64 banks per channel.
  • Supports up to 8 channels per stack.
  • Supports Extended Addressing.
  • Supports Extended Write latency and Read latency.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Commands rules etc.
    • All timing violations.
  • Supports callbacks for user to get command data on bus.
  • Supports All Mode registers programming.
  • Supports DBIac write and read.
  • Supports Legacy Mode and Pseudo Channel Mode Operation (64 DQ width for Pseudo Channel Mode).
  • Supports Self-Refresh Modes.
  • Supports channel density of 1 GB to 128 GB.
  • Supports 128 DQ width + Optional ECC pin support/channel.
  • Supports ECC.
  • Supports write data mask and data strobe features.
  • Supports for power down features.
  • Supports for input clock stop and frequency change.
  • Supports for target row refresh mode.
  • Supports for temperature compensated refresh reporting.
  • Supports for IEEE standard 1500.
  • Bus-accurate timing for min, max and typical values.
  • Constantly monitors HBM behavior during simulation.
  • Protocol Checker fully compliant with HBM Specification JESD235, JESD235A, JESD235B, JESD235C and JESD235D.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of HBM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

HBM Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the HBM testcases.
  • Complete UVM/OVM sequence library for HBM controller.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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