secure execution processor IP
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Secure Execution Processor
- Built-in protection of code and data in a 32-bit compact, low-power, royalty-free, processor IP core.
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Secure Execution Processor
- Two cryptographically isolated secure execution contexts
- Cryptographic primitives agnostic
- Lowest overhead implementation with single Keccak (SHA3) core
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Low power 32-bit processor with secure execution capability
- Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
- Pipeline: 3-stage;
- General register: 16 32-bit GPRs;
- Bus interface: Tri-bus (instruction bus + data bus + system bus) ;
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Ultra-low power 32-bit processor with secure execution capability
- Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
- Pipeline: 2-stage;
- General register: 16 32-bit GPRs;
- Bus interface: Dual bus (instruction bus + data bus);
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Ultra-low power processor with RISC-V architecture possessing secure execution capability
- Instruction set: T-Head ISA (compatible with RV32EMC/RV32EC/RV32IMC);
- Pipeline: 2-stage;
- Permission mode: Optional M state or M+U state;
- General register: 16 32-bit GPRs;
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Performance-efficient, ultra-low power, compact ARC SEM security processors help protect against logical, hardware, physical and side-channel attacks
- ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
- ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
- Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
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Cyber Escort Unit IP provides real time detection of sero day attacks on processor
- Hardware protection on processor
- Compliant with all processor families
- Escort step by step the program execution
- Protection against Cyber attack (ROP, JOP, Buffer overrun, etc.) and Fault Injection attack targeting the code execution
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Root of Trust eSecure module for SoC security
- Secure Boot
- Firmware update in the field
- Secure key storage
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Security Enclave IP based on RISC-V
- Secure Boot
- Firmware update in the field
- Secure key storage
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High-performance 32-bit Superscalar Processor
- Reduced instruction set computer architecture, 32-bit data, 16/32-bit variable length instruction;
