ARC SEM130FS Safety and Security Processor

Overview

The ARC® SEM130FS Safety and Security Processor simplifies development of safety-critical automotive applications while enabling designers to integrate security into their SoC to protect against logical, hardware and physical attacks. The ASIL D compliant SEM130FS processor is a pre-verified dual-core lockstep implementation including a self-checking safety monitor, error correction code (ECC), and a windowed watchdog timer.

The ARC SEM130FS processor includes SecureShield™ technology to enable creation of a Trusted Execution Environment (TEE) to isolate multiple execution contexts and protect secure functions from software vulnerabilities in user code. In addition, the safety and security processor provides protection from side-channel attacks featuring uniform instruction timing, timing randomization and power randomization.

The ARC SEM130FS processor is supported by a comprehensive set of safety work products and the ARC MetaWare Toolkit for Safety with ASIL D Ready certified compiler to generate ISO 26262 compliant code.

Key Features

  • ASIL D compliant dual-core, lockstep safety processor supports ISO 26262 automotive safety standards and provides advanced security to protect against evolving threats
  • Secure privilege mode orthogonal to kernel/user mode
  • Integrated self-checking safety monitor capable of time diversity
  • Uniform instruction timing and timing/ power randomization for side channel resistance
  • Includes hardware safety and security features: ECC, integrated user-programmable windowed watchdog timer, lockstep safety monitor, side-channel protection, fault-injection protection, enhanced memory protection and SecureShield™ technology
  • Performance and area-efficient safe and secure processors for auto and embedded applications
  • MetaWare Toolkit for Safety with ASIL D certified compiler
  • Comprehensive safety documentation eases SoC certification process

Block Diagram

ARC SEM130FS Safety and Security Processor Block Diagram

Technical Specifications

×
Semiconductor IP