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Compare 305 IP from 65 vendors (1 - 10)
  • Aurora-like 64b/66b @14Gbps for ALTERA Devices
    • Full-­Duplex operation.
    • Simplex operation.
    • Up to 14.1Gbps bit rate per lane
    Block Diagram -- Aurora-like 64b/66b @14Gbps for ALTERA Devices
  • Aurora-like 8b/10b @3Gbps for ALTERA Devices
    • Up to 3.125Gbps bit rate per lane
    • Configurable up to 16 transceivers lanes
    • 8B/10B encoding
    • Native flow control with immediate and completion mode
    Block Diagram -- Aurora-like 8b/10b @3Gbps for ALTERA Devices
  • Video Tracking FPGA IP core for Xilinx and Altera
    • MAIN PARAMETERS
    • High processing speed. One video frame processing time: for rectangle 128x128 pixels – 25 ms; for rectangle 128x64 pixels – 13 ms; for rectangle 64x64 pixels – 6,5 ms.
    • Objects tracking from 8x8 pixels to 128x128 pixels and more. Object part tracking.
    • Tracking of objects of very low contrast (from 10%) on a complex background in terms of interference.
  • Video Tracking FPGA IP core for Xilinx and Altera
    • Tracking up to 80 fps at core clock frequency 300 MHz and object size of 128x128 pixels.
    • The IP core implements 1 tracking channel. If sever-al channels are required, several cores need to be used.
  • Video Tracking FPGA IP core for Xilinx and Altera
    • Tracking up to 80 fps at core clock frequency 300 MHz and object size of 128x128 pixels
  • Configurable Multi-Scaler
    • The CMS-1 is a parameterized integration of the VSC-1 scaler core with other IP as needed for ABR and similar applications requiring simultaneous multiple output formats from a single input.
    • The CMS-1 is fully customizable through the use of Verilog parameters so that it may be tailored for use in various applications.
    • The number of simultaneously available outputs, scaler taps, phases, data path and coefficient precision are all configurable. A highly efficient implementation exploits the use of cascading as well as resource sharing in order to minimize implementation cost.
    Block Diagram -- Configurable Multi-Scaler
  • Post-Quantum Key Encapsulation IP Core
    • The PQC-KEM is an IP Core for ML-KEM Key Encapsulation that supports key generation, encapsulation, and decapsulation operations for all ML-KEM variants standardized by NIST in FIPS 203.
    • ML-KEM is a post-quantum cryptographic (PQC) algorithm, designed to be robust against a quantum computer attack.
    Block Diagram -- Post-Quantum Key Encapsulation IP Core
  • SNOW-V Stream Cipher Engine
    • The SNOW-V IP core implements the SNOW-V stream cipher mechanism, aiming to meet the security demands of modern high-speed communication systems.
    • It conforms to the official SNOW-V mechanism, published in 2019 by the IACR Transactions on Symmetric Cryptology, as an extensive revision of SNOW 3G stream cipher.
    Block Diagram -- SNOW-V Stream Cipher Engine
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Semiconductor IP