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Search (13)
Compare 13 IP from 9 vendors (1 - 10)
  • Dual 12-bit 80Msps Low power silicon proven in 28nm ADC IP
    • • Differential analog input
    • • Small footprint
    • • Internal reference generator (no
    • external component)
  • FIR Filter Generator
    • Direct Form 64-Tap FIR Filter: In the direct form FIR filter, the input samples are shifted into a shift register queue and each shift register is connected to a multiplier. The products from the multipliers are added together to get the FIR filter’s output sample. This example shows a 64-tap FIR filter using 16 sysDSP blocks and approximately 512 slices in the LatticeECP3 FPGA.
    • 128-Tap Long Asymmetrical Filters Using Ladder Architecture: Using the ladder architecture, the FIR filter is split into sections each having the same coefficient set as if it was a single continuous filter chain. Instead of connecting the shifted data and the result outputs from the first section to the corresponding input of the next section, the ladder network connects a delayed version of the first stage input data to the second stage input data and sums a delayed version of the first stage sum output with the second stage sum output.
    • 256-Tap Long Symmetrical Filters Using Ladder Architecture: The impulse response for most FIR filters is symmetric. This symmetry can generally be exploited to reduce the arithmetic requirements and produce area-efficient filter realizations. It is possible to use only half the multipliers for symmetric coefficients compared to that used for a similar filter with non-symmetric coefficients. An implementation for symmetric coefficients is shown in the figure below. The 256-tap long symmetrical filter example uses only 32 sysDSP slices, 2EBR and 3.5K slices.
    • Polyphase Interpolator FIR Filter Designs: The polyphase interpolation filter implements the computationally efficient 1-to-P interpolation filter where P is an integer greater than 1. The example below shows a design with an interpolation by 16 that uses 128 taps. This requires 8 polyphase filters (sub-filters) with 16 coefficients each.
    Block Diagram -- FIR Filter Generator
  • Compact and Performance Efficiency 32-bit RISC-V Core
    • AndeStar™ V5 Instruction Set Architecture (ISA)
    • Compliant with RISC-V I, M, A, C, B and Zce extensions
    • Andes extensions for performance and code size enhancements
  • SATA 6G PHY
    • ? 6-Gbps transmission rate through standard SATA cable
    • ? Spread-spectrum clock (SSC) generation and absorption
    • ? Programmable down-spread (+4,980 ppm through -4,980 ppm)
    • ? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY
  • USB 3.0 SSIC Controller
    • Compliant with SSIC v1.01
    • Compliant with M-PHY Specification v2.0
    • Compliant with USB3.0 Pipe Specification
    Block Diagram -- USB 3.0 SSIC Controller
  • Virtex-6 FPGA GTX Transceiver Wizard
    • Creates customized HDL wrappers to configure high-speed serial transceivers
    • Predefined protocol templates support Aurora (8B/10B and 64B/66B), Common Packet Radio Interface (CPRI™), DisplayPort, Fibre Channel, Gigabit Ethernet, High-Definition Serial Digital Interface (HD-SDI), 3 Gb/s Serial Digital Interface (3G-SDI), Interlaken, Open Base Station Architecture Initiative (OBSAI), OC-48, PCI EXPRESS® (PCIe®) generation I and II, Serial Advanced Technology Attachment (SATA) 1.5 Gb/s, SATA 3 Gb/s, Serial RapidIO generation I and II, 10 Gb Attachment Unit Interface (XAUI), and RXAUI-Dune Networks
    • Automatically configures analog settings
  • Virtex-5 FPGA RocketIO GTX Transceiver Wizard
    • Creates customized HDL wrappers to configure high-speed serial transceivers
    • Predefined protocol templates support Aurora (8B/10B and 64B/66B), CPRI™, Fibre Channel 1x, Gigabit Ethernet, HD-SDI, OBSAI, OC3, OC12, OC48, PCI EXPRESS® (PCIe®) Generation I and II, SATA 1.5 Gbps, SATA 3 Gbps, Serial RapidIO, and XAUI
    • Automatically configures analog settings
  • High Data Rate Modulator
    • Versatile digital modulation engine
    • Programmable constellation mapper supports multiple constellations from BPSK to 256QAM
    • Supports offset-QPSK (OQPSK)
    • Supports continuously variable symbol rates
  • 10bit 1Msps SAR ADC IP Core
    • 10-bit Parallel Output.
    • Conversion time/Sampling frequency = 1 us/ 1Msps
    • CLOCK REQUIREMENT: 2 MHz- 20 MHz
    Block Diagram -- 10bit 1Msps SAR ADC IP Core
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