Universal TV Encoder IP
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431
IP
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53
vendors
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10)
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Universal Serial 10GE Media Independent Interface (USXGMII)
- The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC).
- Link speeds of 5G, 10G, or 20G are supported. Compliant with the Cisco Universal SXGMII Interface for multiple Multi-Gigabit Copper Network Ports and IEEE 802.3 Clause 49 standards, the PCS IP has several optional features to customize the physical coding sublayer (PCS) for the specific needs of any application.
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Universal Chiplet Interconnect Express(UCIe) VIP
- The UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs
- The UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols
- The UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters
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UCIe and BOW Universal PHY
- Novel Redundancy for Hi-Rel,
- Support for 16&18-bit wide data,
- Support Synchronous Operation,
- Supports Advanced packaging,
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DCD's Universal Timers System
- PWM:
- Timer 1:
- Timer 2:
- Timer 3:
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CLICK - The universal solution of power gating for the whole SoC
- Flexibility of in-rush current and wake-up time management
- Allows a smart control of the trade-off between wake-up time and in-rush current
- Automated wake-up sequence including isolation and retention signal management
- Programmable limitation of in-rush current controlled by Transition Ramp Controller enables a ? correct-by-construction ? implementation
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CLICK - The universal solution of power gating for the whole SoC
- Flexibility of in-rush current and wake-up time management
- Allows a smart control of the trade-off between wake-up time and in-rush current
- Automated wake-up sequence including isolation and retention signal management
- Programmable limitation of in-rush current controlled by Transition Ramp Controller (TRC) enables a ? correct-by-construction? implementation
-
CLICK - The universal solution of power gating for the whole SoC
- Flexibility of in-rush current and wake-up time management
- Allows a smart control of the trade-off between wake-up time and in-rush current
- Automated wake-up sequence including isolation and retention signal management
- Programmable limitation of in-rush current controlled by Transition Ramp Controller (TRC) enables a ?correct-by-construction? implementation
-
CLICK - The universal solution of power gating for the whole SoC
- Flexibility of in-rush current and wake-up time management
- Allows a smart control of the trade-off between wake-up time and in-rush current
- Automated wake-up sequence including isolation and retention signal management
- Programmable limitation of in-rush current controlled by Transition Ramp Controller (TRC) enables a ? correct-by-construction ? implementation
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Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)
- Programmable application-side FIFO sizes (or complete bypass ) on TX, RX or both for easy integration with application logic
- Packing and unpacking logic for application to internal data path matching
- Supports line rate with minimum IFG
- Memory-based statistics counter implementation for Area/gate savings
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0.6G - 12.5G Universal SerDes
- 0.6Gbps to 12.5Gbps universal SERDES IP
- Support full, 1/2, 1/4 and 1/8 data rate mode
- Support up to 12 TX/RX data lanes with shared PMU
- Fractional PLL for wide data rate range selection