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TSMC 5nm IP

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Compare 100 IP from 8 vendors (1 - 10)
  • PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet
    • DSP-based Long Reach (LR) equalization and clock data recovery (CDR) provide superior performance and reliability
    • Low active and standby power consumption, supports L1 sub-states standby power management
    • Extensive set of isolation, test modes, and loopbacks including APB and JTAG
    • Supports lane aggregation and bifurcation
  • 112G-ELR PAM4 SerDes PHY - TSMC 5nm
    • TSMC 5nm FinFET CMOS Process
    • Power-optimized for ELR and LR links
    • Integrated BIST capable of producing and checking PRBS
    • 56-112Gbps PAM4 or 1-56Gbps NRZ data rates
  • PHY for PCIe 5.0 and CXL for TSMC 5nm FinFet
    • High-performance PHY for data center applications
    • Low-latency, long-reach, and low-power modes
    • Wide range of protocols that support networking, storage, and computing applications
    • Multi-protocol support for application flexibility
  • USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
    • Complies with USB specifications Rev. 2.0 and 1.1
    • Complies with UTMI+ specification Level 3, Rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
    Block Diagram -- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
  • MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
    • Compliant to MIPI Alliance Standard for C-PHY specification Version 1.2
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    Block Diagram -- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
  • MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
    • Compliant to MIPI for C-PHY specification Version 1.2
    • Compliant to MIPI for D-PHY specification Version 1.2
    Block Diagram -- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
  • MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
    • Supports standard PHY transceiver compliant to MIPI Specification
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
    Block Diagram -- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
  • TSMC 5nm (N5) 1.2V/1.8V Basekit Libraries
    • Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
    • Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
    • Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
    • Supports retention and bus-keeper feature
  • TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks
    • Completely hardened PHY solution along with programmable delay chains & I/Os
    • Fully selectable output impedance
    • Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
    • Automotive G1/G2 supported, ASIL-B certified
  • TSMC 5nm (N5) 1.8V SD/eMMC PHY
    • Completely hardened PHY solution along with programmable delay chains & I/Os
    • Fully selectable output impedance
    • Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
    • Automotive G1/G2 supported, ASIL-B certified
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