TSMC 10nm FinFET IP
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32
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8
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DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
- The DDR5&DDR4 COMBO IO is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the DRAM device
- The TX is designed to send information from PHY to DRAM and RX is designed to receive information which is from DRAM._x000D_ It supports DDR5&DDR4 interface
- The DDR5 DQ data rate can be up to 4800Mb/s, and the DDR4 DQ data rate can be up to 3200Mb/s and CA is SDR mode.
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MIPI D-PHY Tx-Only 4 Lanes in TSMC (16nm) for Automotive
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Tx-Only 2 Lanes in TSMC (16nm) for Automotive
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Bidirectional 4 Lanes in TSMC (40nm, 28nm, 16nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Bidirectional 2 Lanes in TSMC (40nm, 28nm, 16nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P)
- Compliant with the latest MIPI C-PHY and D-PHY specifications
- Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
- D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
- C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes
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MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
- Compliant with the latest MIPI C-PHY and D-PHY specifications
- Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
- D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
- C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes
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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
- Compliant with the latest MIPI C-PHY and D-PHY specifications
- Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
- D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
- C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes