Sarnoff IP
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11
IP
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Single Rail SRAM GLOBALFOUNDRIES 22FDX
- Single port SRAM compiler based on Racyics® R188 logic memory cell with dual-well architecture
- Supply voltage 0.55 V to 0.8 V enabled with Racyics® ABB
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Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
- Contains >300 cells, various Vt and channel length options
- Robust power supply rails on M2, optimized M1 pin access with at least two on-track M2 access points
- DFM and variability optimized layouts and variation aware placement attributes for automated place&route
- Enabled for reliable ULV operation down to 0.4 V in combination with adaptive forward body bias
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Dual-Rail SRAM Globalfoundries 22FDX
- Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
- Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
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SMIC 0.18¦Ìm 1.8v/3.3v Power Switch
- Process: SMIC 0.18¦Ìm 1.8v/3.3v Logic process
- Operating current: up to 20mA
- Voltage drop: less than 20mV @ 20mA
- Turn-on latency time is less than 100ns
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PUF Base/Premium
- Proven and mature PUF solution and world’s first IP to be awarded “PSA Certified Level 3 RoT Component and SESIP Level 3”
- Uses standard SRAM power-up values as a PUF and is quantum safe
- Offers key provisioning, wrapping, and unwrapping to enable secure key storage across the supply chain and for the entire lifetime of the device
- Keys are never stored, but re-created from the PUF each time they are needed, offering a higher level of security than traditional key storage in NVM
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12-bit 1Msps Very low power SAR ADC silicon proven in 28nm
- • 12-bit SAR ADC up-to 1MS/s conversion rate.
- • Zero DC power
- • Single-ended/ Differential input
- • 4-input channels
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Wi-Fi 802.11 ax/Wi-Fi 6 /Bluetooth LE v5.4/15.4-2.4GHz RF Transceiver IP for IOT Application in TSMC22 ULL
- Metal Layer- 1P7M, 4X1Z1U
- BW support for 20/ 40MHz
- Supports 256 QAM (quadrature amplitude modulation)
- Max Tx output power: +20dBm
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2.5Gbps Ethernet MAC IP Core
- Compliant to IEEE 802.3-2005 standard
- Generic 8-bit host interface
- 16-bit wide internal data path
- Generic transmit and receive FIFO interface
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Gigabit Ethernet Media Access Controller
- Data Link Layer
- Programmable 10/100 or 1000 Mbps operation
- IEEE 802.3-2002 specification with preamble, start-of-frame delimiter (SFD), and CRC generation and checking
- Full- or half-duplex operation
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MAC 10/100/1000 Ethernet Controller
- IEEE 802.3-2002 specification with preamble, start-of-frame delimiter (SFD), frame padding generation and cyclic redundancy code (CRC) generation and checking is fully implemented
- Supports 10/100 Mbps or 1000 Mbps operation (selectable via a core configuration registers)
- Supports full- and half-duplex operation (selectable via a core configuration registers)
- CSMA/CD protocol for half-duplex operation